AT89C51CC03C-RDTIM Atmel, AT89C51CC03C-RDTIM Datasheet - Page 71
AT89C51CC03C-RDTIM
Manufacturer Part Number
AT89C51CC03C-RDTIM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-RDTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CRDTIM
- AT89C51CC03C-S3RIM PDF datasheet
- AT89C51CC03C-S3RIM PDF datasheet #2
- AT89C51CC03C-S3RIM PDF datasheet #3
- AT89C51CC03C-S3RIM PDF datasheet #4
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- Download datasheet (7Mb)
Mode 2 (8-bit Timer with Auto-
Reload)
Figure 37. Timer/Counter x (x = 0 or 1) in Mode 2
Mode 3 (Two 8-bit Timers)
Figure 38. Timer/Counter 0 in Mode 3: Two 8-bit Counters
4182E–CAN–05/04
See the “Clock” section
INT0#
See the “Clock” section
INTx#
CLOCK
CLOCK
CLOCK
T0
FTx
Tx
FTx
FTx
TMOD reg
GATEx
GATE0
TMOD.3
÷ 6
÷ 6
÷ 6
TMOD reg
TMOD.2
C/T0#
C/Tx#
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, which is preset by software. When the interrupt
request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next
reload value may be changed at any time by writing it to TH0 register.
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see Figure 38). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting F
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
3.
0
1
0
1
TCON reg
TCON.4
TR0
TRx
TCON.6
TR1
PER
/6) and takes over use of the Timer 1 interrupt (TF1) and
(8 bits)
(8 bits)
(8 bits)
(8 bits)
TH0
THx
TL0
TLx
Overflow
Overflow
Overflow
TCON reg
TCON.5
TCON.7
TF0
TF1
TFx
AT89C51CC03
Timer x
Interrupt
Request
Timer 0
Interrupt
Request
Timer 1
Interrupt
Request
71
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