AT89C51CC03C-RDTIM Atmel, AT89C51CC03C-RDTIM Datasheet - Page 88
![IC 8051 MCU FLASH 64K 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C51CC03C-RDTIM
Manufacturer Part Number
AT89C51CC03C-RDTIM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-RDTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CRDTIM
- AT89C51CC03C-S3RIM PDF datasheet
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Bit Shortening
Synchronization Jump Width
Programming the Sample Point
Arbitration
Errors
Error at Message Level
88
AT89C51CC03
If, on the other hand, the transmitter oscillator is faster than the receiver one, the next
falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N
is shortened in order to adjust the sample point for bit N+1 and the end of the bit time
The limit to the amount of lengthening or shortening of the Phase Segments is set by the
Resynchronization Jump Width.
This segment may not be longer than Phase Segment 2.
Programming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchroniza-
tion Jump Width can be programmed to its maximum. This maximum capacity to
shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances,
so that lower cost oscillators such as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows
a poorer bus topology and maximum bus length.
Figure 46. Bus Arbitration
The CAN protocol handles bus accesses according to the concept called “Carrier Sense
Multiple Access with Arbitration on Message Priority”.
During transmission, arbitration on the CAN bus can be lost to a competing device with
a higher priority CAN Identifier. This arbitration concept avoids collisions of messages
whose transmission was started by more than one node simultaneously and makes sure
the most important message is sent first without time loss.
The bus access conflict is resolved during the arbitration field mostly over the identifier
value. If a data frame and a remote frame with the same identifier are initiated at the
same time, the data frame prevails over the remote frame (c.f. RTR bit).
The CAN protocol signals any errors immediately as they occur. Three error detection
mechanisms are implemented at the message level and two at the bit level:
•
•
Cyclic Redundancy Check (CRC)
The CRC safeguards the information in the frame by adding redundant check bits at
the transmission end. At the receiver these bits are re-computed and tested against
the received bits. If they do not agree there has been a CRC error.
Frame Check
This mechanism verifies the structure of the transmitted frame by checking the bit
CAN bus
TXCAN
TXCAN
node A
node B
SOF
SOF
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Arbitration lost
Node A loses the bus
Node B wins the bus
RTR IDE
- - - - - - - - -
4182O–CAN–09/08
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