MCIMX258CJM4A Freescale Semiconductor, MCIMX258CJM4A Datasheet - Page 96

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MCIMX258CJM4A

Manufacturer Part Number
MCIMX258CJM4A
Description
IC MPU IMX25 IND 400MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Datasheet

Specifications of MCIMX258CJM4A

Core Processor
ARM9
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
External Program Memory
Ram Size
144K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.52 V
Data Converters
A/D 3x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
400-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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0
1
3.7.14
Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals).
Typically a port uses five signals.
The interface is designed to be used with synchronous SIM cards, meaning the SIM module provides the
clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the
SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard
UART data exchanges. All six signals (five for bidirectional Tx/Rx) of the SIM module are asynchronous
with each other.
There are no required timing relationships between signals in normal mode. The SIM card is initiated by
the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no
defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed
information see ISO/IEC 7816).
96
CL of PWMO = 30 pF
Ref No.
2a
2b
3a
3b
4a
4b
1
Subscriber Identity Module (SIM) Timing
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
PWM Source Clock
System CLK frequency
PWM Output
Output setup time
Output delay time
Clock high time
Clock rise time
Clock low time
Clock fall time
Parameter
Table 73. PWM Output Timing Parameter
Figure 67. PWM Timing
1
4a
2a
2b
Minimum
12.29
9.91
8.71
0
3a
1
Maximum
ipg_clk
9.37
0.5
0.5
3b
4b
Freescale Semiconductor
MHz
Unit
ns
ns
ns
ns
ns
ns

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