AT91SAM7S128C-MU Atmel, AT91SAM7S128C-MU Datasheet - Page 348
![IC MCU ARM7 128K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT91SAM7S128C-MU
Manufacturer Part Number
AT91SAM7S128C-MU
Description
IC MCU ARM7 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S128C-MU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Core
ARM7TDMI
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S128-MU
AT91SAM7S128-MU
AT91SAM7S128-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S128C-MU
Manufacturer:
ATMEL
Quantity:
670
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- Download datasheet (11Mb)
30.10.6
Name:
Access:
Reset Value: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 339
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 339
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
348
31
23
15
–
–
7
–
AT91SAM7S Series Preliminary
and
and
TWI Status Register
TWI_SR
Read-only
Figure 30-30 on page
Figure 30-30 on page
OVRE
30
22
14
–
–
6
GACC
339.
339.
29
21
13
–
–
5
Figure 30-8 on page
Figure 30-10 on page
Figure 30-25 on page
SVACC
Figure 30-27 on page
Figure 30-8 on page 320
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
320.
321.
335,
337,
and in
Figure 30-28 on page
Figure 30-28 on page
SCLWS
TXRDY
26
18
10
Figure 30-10 on page
–
–
2
ARBLST
RXRDY
25
17
–
–
9
1
338,
338,
6175K–ATARM–30-Aug-10
321.
Figure 30-29 on
Figure 30-29 on
TXCOMP
NACK
24
16
–
–
8
0
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