CY8C3246PVA-141 Cypress Semiconductor Corp, CY8C3246PVA-141 Datasheet - Page 31

• Manufacturer Part Number: CY8C3246PVA-141
• Description: IC MCU 8BIT 64KB FLASH 48SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246PVA-141

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Document Number: 001-56955 Rev. *J
Active
Alternate
Active
Sleep
Hibernate
Note
Power Modes
Active
Alternate
Active
Sleep
Hibernate
12. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See
Active
Alternate Active
Sleep
Hibernate
Modes
Sleep
and
Wakeup
<100 µs
<15 µs
Table
Time
Primary mode of operation, all
peripherals available (program-
mable)
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
–
–
6-3. The power modes allow a design to
1.2 mA
Current
Description
200 nA
(typ)
1 µA
–
[12]
Execution
defined
Code
User
Yes
No
No
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
Resources
Digital
None
Table 11-2
I
All
All
2
C
on page 63.
Comparator
Resources
Any interrupt
Any interrupt
Comparator,
PICU, I
CTW, LVD
PICU
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins.
power modes.
Analog
None
All
All
Figure 6-5
2
C, RTC,
Clock Sources
ILO/kHzECO
Available
illustrates the allowable transitions between
None
Any
(programmable)
Any
(programmable)
ILO/kHzECO
All
All
Active Clocks
PSoC
Wakeup Sources
®
PICU, I
Comparator,
3: CY8C32 Family
CTW, LVD
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
PICU
2
–
–
C, RTC,
Data Sheet
Regulator
Page 31 of 119
XRES, LVD,
Sources
Reset
XRES
WDR
All
All
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