73S1210F-44IMR/F Maxim Integrated Products, 73S1210F-44IMR/F Datasheet - Page 33
73S1210F-44IMR/F
Manufacturer Part Number
73S1210F-44IMR/F
Description
IC SMART CARD READER 44-QFN
Manufacturer
Maxim Integrated Products
Datasheet
1.73S1210F-44MFPC.pdf
(126 pages)
Specifications of 73S1210F-44IMR/F
Core Processor
80515
Core Size
8-Bit
Speed
24MHz
Connectivity
I²C, SmartCard, UART/USART
Peripherals
LED, POR, WDT
Number Of I /o
8
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
1210x
Core
80515
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
73S1210F-EB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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DS_1210F_001
1.7.5
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These are described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1210F, for example the USR I/O, smart card interface, analog comparators, etc. The external
interrupt configuration is shown in Figure 9.
Rev. 1.4
Interrupts
VCC_OK
Card_Det
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
KeyPad
Serial
Serial
INT3
Analog
Ch 0
Ch 1
INT2
Comp
I
2
VccCTL
CRDCtl
C
Figure 9: External Interrupt Configuration
Pads
Pads
USR
INT
+
VDD_Fault
Card Event
VCC_TMR
USR
USR
Int
Ctl
Wait Timeout
USR
Int
Ctl
Ctl
USR
Int
Ctl
Int
TX_Event
RX_Error
TX_Error
Tx_Sent
RxData
INT5
INT6
PDMUXCtl
Ctl
Ctl
SCInt
when PWRDN bit is set
During STOP, IDLE
+
SCIE
Delay
0
1
+
t0
int4
int5
int6
SerChan 0 int
SerChan 1 int
int0
t1
int1
int2
int3
Clear PWRDN bit
CORE
MPU
73S1210F Data Sheet
33
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