73S1210F-44IMR/F Maxim Integrated Products, 73S1210F-44IMR/F Datasheet - Page 59
73S1210F-44IMR/F
Manufacturer Part Number
73S1210F-44IMR/F
Description
IC SMART CARD READER 44-QFN
Manufacturer
Maxim Integrated Products
Datasheet
1.73S1210F-44MFPC.pdf
(126 pages)
Specifications of 73S1210F-44IMR/F
Core Processor
80515
Core Size
8-Bit
Speed
24MHz
Connectivity
I²C, SmartCard, UART/USART
Peripherals
LED, POR, WDT
Number Of I /o
8
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
1210x
Core
80515
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
73S1210F-EB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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DS_1210F_001
I2C Secondary Read Data Register (SRDR): 0XFF84 0x00
I2C Control and Status Register (CSR): 0xFF85 0x00
Rev. 1.4
CSR.7
CSR.6
CSR.5
CSR.4
CSR.3
CSR.2
CSR.1
CSR.0
MSB
MSB
Bit
SRDR.7
SRDR.7
SRDR.6
SRDR.5
SRDR.4
SRDR.3
SRDR.2
SRDR.1
SRDR.0
Bit
–
Symbol
I2CLEN
AKERR
Second Data byte to be read from the I
and Status register (CSR) is set = 1.
I2CST
SRDR.6
–
–
–
–
–
–
Set to 1 if acknowledge bit from Slave Device is not 0. Automatically reset
when the new bus transaction is started.
Write a 1 to start I
transaction is done. This bit should be treated as a “busy” indicator on
reading. If it is high, the serial read/write operations are not completed and
no new address or data should be written.
Set to 1 for 2 byte read or write operations. Set to 0 for 1-byte operations.
SRDR.5
–
Table 61: The SRDR Register
Table 62: The CSR Register
SRDR.4
–
2
C transaction. Automatically reset to 0 when the bus
SRDR.3
Function
2
–
C slave device if bit 0 (I2CLEN) of the Control
Function
AKERR
SRDR.2
SRDR.1
I2CST
73S1210F Data Sheet
SRDR.0
I2CLEN
LSB
LSB
59
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