71M6511-IGTR/F Maxim Integrated Products, 71M6511-IGTR/F Datasheet - Page 11

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71M6511-IGTR/F

Manufacturer Part Number
71M6511-IGTR/F
Description
IC ENERGY METER RESIDENT 64-LQFP
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet

Specifications of 71M6511-IGTR/F

Mounting Style
SMD/SMT
Package / Case
LQFP-64
Core
80515 MPU
Data Bus Width
32 bit
Data Ram Size
7 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
UART
Maximum Clock Frequency
70 Hz
Maximum Operating Temperature
+ 85 C
Number Of Programmable I/os
12
Operating Supply Voltage
3.3 V
Processor Series
71M6511
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
71M6511-IGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
Computation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.
The CE calculations and processes include:
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word
is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code
pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the
multiplexer cycle ends (see System Timing Summary in the Functional Description Section).
The CE data RAM (CE DRAM) can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding re-
gisters are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed,
depending on the frequency of CKMPU.
Table 3 shows the CE DRAM addresses allocated to analog inputs from the AFE.
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Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between samples caused
by the multiplexing scheme).
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on chip temperature (temperature compensation) and calibration
coefficients.
© 2005–2010 Teridian Semiconductor Corporation
Figure 3: AFE Block Diagram
Single-Phase Energy Meter IC
71M6511/71M6511H
DATA SHEET
NOVEMBER 2010
V2.7

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