71M6531D-IMR/F Maxim Integrated Products, 71M6531D-IMR/F Datasheet - Page 91
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71M6531D-IMR/F
Manufacturer Part Number
71M6531D-IMR/F
Description
IC ENERGY METER 128KB 68-QFN
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6531D-IMRF.pdf
(120 pages)
Specifications of 71M6531D-IMR/F
Mounting Style
SMD/SMT
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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FDS 6531/6532 005
v1.3
CECONFG
Address
Address
[15:8]
0x24
0x40
[bit]
[19]
[18]
[17]
[16]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
CE
CE
PULSE_SLOW 0
PULSE_FAST
SAG_MASK1
SAG_MASK0
EXT_PULSE
EXT_TEMP
FREQSEL1
FREQSEL0
IB_SHUNT
IA_SHUNT
SAG_CNT
SAG_INT
Name
GAIN_ADJ
SAG_THR
–
Name
Name
© 2005-2010 TERIDIAN Semiconductor Corporation
Default
(0x50)
Table 58: CECONFIG Bit Definitions
80
0
0
0
0
0
0
1
0
0
0
0
Table 59: Sag Threshold Control
Default
443000
Default
16384
Table 60: Gain Adjust Control
Sets the sag control of phase B.
Sets the sag control of phase A.
If more than one sag mask is set, a sag interrupt will only be
generated when all phases enabled for the interrupt sag.
When set, enables the sag interrupt to be output on the
YPULSE/DIO9 pin.
When set, enables the control of GAIN_ADJ by the MPU.
When 0, enables the control of GAIN_ADJ by the CE.
The number of consecutive voltage samples below SAG_THR
before a sag alarm is declared. The maximum value is 255.
SAG_THR is at address 0x24.
The combination of FREQSEL1 and FREQSEL0 selects the phase
to be used for the frequency monitor, the phase-to-phase lag
calculation, the zero-crossing counter MAINEDGE_X and the
F0 bit (CESTATUS[28]).
FREQSEL1/FREQSEL0 = 0/0: Phase A
FREQSEL1/FREQSEL0 = 0/1: Phase B
When zero, causes the pulse generators to respond to internal
data (PULSE0 = WSUM_X, PULSE1 = VARSUM_X., PULSE2 =
VASUM_X). Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
Unused.
When 1, the current gain of channel B is increased by 8. The
gain factor controlled by In_SHUNT is referred to as In_8
throughout this document.
When 1, the current gain of channel A is increased by 8.
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two bits control the pulse
gain factor X (see table below). Default is 0 for both (X = 6).
PULSE_SLOW PULSE_FAST
The threshold for sag warnings. The default value is
equivalent to 80 V RMS if VMAX = 600 V. The LSB value
is VMAX * 4.255*10
This register scales all voltage and current channels. The
default value is equivalent unity gain (1.000).
0
0
1
1
0
1
0
1
-7
Data Sheet 71M6531D/F-71M6532D/F
Description
V (peak).
Description
Description
1.5 * 2
1.5 * 2
1.5 * 2
Do not use
2
6
-4
= 6
= 96
= 0.09375
X
91
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