71M6513-IGTR/F Maxim Integrated Products, 71M6513-IGTR/F Datasheet - Page 62

• Manufacturer Part Number: 71M6513-IGTR/F
• Description: IC ENERGY METER 3PH 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6513-IGTR/F

• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Supply Current (max): 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
DIO_0[7:0]
DIO_1[7:0]
DIO_2[5:0]
DIO_EEX
DIO_PV
DIO_PW
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
EQU[2:0]
EX_XFR
EX_RTC
FIR_LEN
FLASH66Z
FLSH_ERASE
FLSH_MEEN
Page: 62 of 104
A Maxim Integrated Products Brand
Location
[Bit(s)]
SFR 80
SFR 90
SFR
A0[5:0]
2008[4]
2008[2]
2008[3]
SFR 9E
SFR 9F
2005[5]
2000[7:5]
2002[0]
2002[1]
2005[4]
2005[1]
SFR 94
SFR B2[1]
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
W
© 2005-2011 Teridian Semiconductor Corporation
Description
Port 0
Port 1
Port 2
When set, converts DIO4 and DIO5 to interface with external EEPROM.
DIO4 becomes SCK and DIO5 becomes bi-directional SDA. LCD_NUM
must be less than 18.
Causes VARPULSE to be output on DIO7, if DIO7 is configured as output.
LCD_NUM must be less than 15.
Causes WPULSE to be output on DIO6, if DIO6 is configured as output.
LCD_NUM must be less than 16.
Serial EEPROM interface data
Serial EEPROM interface control
Emulator clock disable. When one, the emulator clock is disabled. This bit
is set, it should be done at least 1000ms after power-up to give emulators
and programming devices enough time to complete an erase operation.
Specifies the power equation to the CE.
Interrupt enable bits. These bits enable the XFER_BUSY and the
RTC_1SEC interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),
0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)
Should be set to 1 to minimize supply current.
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the
Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in
order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to
Any other pattern written to FLSH_ERASE will have no effect.
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
FLSH_PGADR @ SFR 0xB7.
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be
enabled.
is to be used with caution! Inadvertently setting this bit will
inhibit access to the part with the ICE interface and thus
preclude flash erase and programming operations. If ECK_DIS
3-Phase Energy Meter IC
The value on the DIO pins. Pins configured
as LCD will read zero. When written,
changes data on pins configured as out-
puts. Pins configured as LCD or input will
ignore writes.
71M6513/71M6513H
DATA SHEET
AUGUST 2011