73M1866B-IFX Maxim Integrated Products, 73M1866B-IFX Datasheet - Page 3

• Manufacturer Part Number: 73M1866B-IFX
• Description: KIT EVALUATION FOR 73M1866B
• Manufacturer: Maxim Integrated Products

Specifications of 73M1866B-IFX

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN_1x66B_003
connection should be provided with copper on the top and bottom connected with PCB vias to stitch the two
layers together.
The 73M1966B Demo Board layout is illustrated in
in Figure 7 and Figure 8. A minimum of 0.5 square inch of copper should be used on both the top and bottom
layers. In current-limit mode under worst-case conditions, over 2.4 W will be dissipated by Q6 (60 mA @ >40 V).
If the current-limit mode is used, a higher-power transistor with heat sinking will be necessary. SOT223 power
transistor packages cannot be used at these power levels, so an NPN transistor with a package able to dissipate at
least 2.4 W and with a minimum beta of 60 (for example, the Fairchild KSD1273) must be used for Q6.
Power Supply Considerations
It is recommended that ground and power planes be used on the host-side to help minimize EMI and noise. To
improve Electromagnetic Compatibility (EMC), we do not recommend the use of ground and power planes on the
line-side. Line-side circuits are predominately analog, not high-speed digital, and generally do not benefit from
the use of power and ground planes.
Power supply considerations include the following:
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Rev. 3.5
Do not use power and ground planes on the line-side circuit.
Use power and ground planes on the host-side circuit.
Pay special attention to the way the power and bypass capacitors are connected to the 73M1866B/1966B, as
in Figure 3 A. PCB traces from the bypass capacitors to the VDD positive supply should be kept as short as
possible.
Keep all bypass capacitors close to the VDD power pins of the device. Ensure that the VDD supply is routed
through the bypass capacitor pad and that the GND connection is direct to GND using several vias.
The power and ground traces should be at least 0.5 mm.
Power and ground traces for analog and digital supplies should be separated for best low-level receive
performance. Power to digital pins and associated bypass capacitors should be kept separate from analog
power and bandgap reference (VBG) bypass pins, by using separate traces.
Use 1000 pF capacitors on power supply pins to minimize EMI and place them near the connecting pins.
VDD
A
Figure 3: Layout and Routing of Power/Bypass Capacitors
GND
73M1906B /
VDD
Protection
73M1916
Bypass/
Device
Figure 6
versus
73M1866B/73M1966B Schematic and Layout Guidelines
with corresponding top and bottom layer routing shown
GND
B
VDD
73M1906B /
Protection
VDD
Bypass/
73M1916
Device
3