M52277EVB Freescale Semiconductor, M52277EVB Datasheet - Page 35

• Manufacturer Part Number: M52277EVB
• Description: BOARD DEMO FOR MCF5227
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: MCUr

Specifications of M52277EVB

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: Coldfire
• Core Sub-architecture: Coldfire V2
• Silicon Core Number: MCF52
• Silicon Family Name: MCF5227x
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MCF52277
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
1
2
3
1
Num
Num
S10
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not
exceed 4 x f
S11
S12
S13
S14
S15
S16
S17
S18
All timings specified with a capactive load of 25 pF.
S5
S6
S7
S8
S9
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
SSI_RXD / SSI_FS input hold after SSI_BCLK
SSI_BCLK cycle time
SSI_BCLK to SSI_TXD / SSI_FS output valid
SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
SSI_BCLK pulse width high / low
SSI_FS input setup before SSI_BCLK
SSI_FS input hold after SSI_BCLK
SSI_RXD setup before SSI_BCLK
SSI_RXD hold after SSI_BCLK
SYS
.
MCF5227x ColdFire
Characteristic
Characteristic
Table 26. SSI Timing—Master Modes
Table 27. SSI Timing—Slave Modes
®
Microprocessor Data Sheet, Rev. 8
Symbol
Symbol
t
BCLK
1
(continued)
4 × 1/f
1
45%
Min
Min
10
10
10
—
—
—
0
0
0
2
0
2
SYS
Max
Max
55%
10
10
—
—
—
—
—
—
—
10
—
—
—
Electrical Characteristics
t
Unit
Unit
BCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
35