CK-V6-ML623-G Xilinx Inc, CK-V6-ML623-G Datasheet - Page 17

• Manufacturer Part Number: CK-V6-ML623-G
• Description: BOARD DEV V6 WITH TX
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 LXTr
• Type: FPGAr

Specifications of CK-V6-ML623-G

• Contents: Board, Cables, Documentation, Power Supply
• For Use With/related Products: Virtex™ 6 LXT, XC6VLX240T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ML623 Board User Guide
UG724 (v1.1) September 15, 2010
200 MHz 2.5V LVDS Oscillator
Single-Ended SMA Global Clock Inputs
X-Ref Target - Figure 1-6
Table 1-4
Table 1-4: JTAG Isolation Jumpers
[Figure
The ML623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1 – 3 and 2 – 4 (LVDS).
Table 1-5: LVDS Oscillator Global Clock Connections
[Figure
The ML623 board provides two single-ended clock input SMA connectors that can be used
for connecting to an external function generator. The FPGA clock pins are connected to the
SMA connectors as shown in
To use these clock inputs, remove jumpers across AFX SEL headers J186 and J187.
Reference Designator
FPGA Pin
1-2, callout 10]
1-2, callout 11]
indicates the FPGA pin name associated with each jumper.
H9
J9
J195
J196
J22
J23
FPGA
IO_LVDS_CLK_N
IO_LVDS_CLK_P
U1
Figure 1-6: JTAG Isolation Jumpers
www.xilinx.com
Table 1-5
Net Name
FPGA Pin Name
Table
TDO
TMS
TCK
TDI
TMS
TDO
TCK
TDI
1-6.
lists the FPGA pin connections to the LVDS oscillator.
J196
J195
J23
J22
U7 Pin
4
5
CFGTCK
CFGTDI
CFGTDO
CFGTMS
System ACE
Controller
UG724_c1_06_040610
U25
Detailed Description
17