CK-V6-ML623-G Xilinx Inc, CK-V6-ML623-G Datasheet - Page 49

• Manufacturer Part Number: CK-V6-ML623-G
• Description: BOARD DEV V6 WITH TX
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 LXTr
• Type: FPGAr

Specifications of CK-V6-ML623-G

• Contents: Board, Cables, Documentation, Power Supply
• For Use With/related Products: Virtex™ 6 LXT, XC6VLX240T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ML623 Master UCF Listing
ML623 Board User Guide
UG724 (v1.1) September 15, 2010
The ML623 master user constraints file (UCF) template provides for designs targeting the
ML623 Virtex-6 FPGA GTX transceiver characterization board. Net names in the
constraints listed below correlate with net names on the ML623 board schematic. Users
must identify the appropriate pins and replace the net names below with net names in the
user RTL. See the
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connectors J112,
J113, and J115 are connected to 2.5V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
ML623 Master UCF Listing:
NET "112_REFCLK0_N"
NET "112_REFCLK0_P"
NET "112_REFCLK1_N"
NET "112_REFCLK1_P"
NET "112_RX0_N"
NET "112_RX0_P"
NET "112_RX1_N"
NET "112_RX1_P"
NET "112_RX2_N"
NET "112_RX2_P"
NET "112_RX3_N"
NET "112_RX3_P"
NET "112_TX0_N"
NET "112_TX0_P"
NET "112_TX1_N"
NET "112_TX1_P"
NET "112_TX2_N"
NET "112_TX2_P"
NET "112_TX3_N"
NET "112_TX3_P"
NET "113_REFCLK0_N"
NET "113_REFCLK0_P"
NET "113_REFCLK1_N"
NET "113_REFCLK1_P"
NET "113_RX0_N"
NET "113_RX0_P"
NET "113_RX1_N"
NET "113_RX1_P"
NET "113_RX2_N"
NET "113_RX2_P"
NET "113_RX3_N"
Constraints Guide
www.xilinx.com
for more information.
cco
LOC = "AK5";
LOC = "AK6";
LOC = "AH5";
LOC = "AH6";
LOC = "AP6";
LOC = "AP5";
LOC = "AM6";
LOC = "AM5";
LOC = "AL4";
LOC = "AL3";
LOC = "AJ4";
LOC = "AJ3";
LOC = "AP2";
LOC = "AP1";
LOC = "AN4";
LOC = "AN3";
LOC = "AM2";
LOC = "AM1";
LOC = "AK2";
LOC = "AK1";
LOC = "AD5";
LOC = "AD6";
LOC = "AB5";
LOC = "AB6";
LOC = "AG4";
LOC = "AG3";
LOC = "AF6";
LOC = "AF5";
LOC = "AE4";
LOC = "AE3";
LOC = "AC4";
banks. Because each user’s FMC card implements
Appendix C
49