AD6620S/PCB Analog Devices Inc, AD6620S/PCB Datasheet - Page 2

• Manufacturer Part Number: AD6620S/PCB
• Description: BOARD EVAL DUAL RCVR W/AD6620AS
• Manufacturer: Analog Devices Inc

Specifications of AD6620S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6620

TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13
INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 19
SECOND ORDER CASCADED INTEGRATOR
FIFTH ORDER CASCADED INTEGRATOR
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25
CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27
PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 30
ACCESS PROTOCOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 32
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 35
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 37
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44
AD6620
SYNC NCO
SYNC RCF
EXP[2:0]
IN[15:0]
SYNC CIC
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16
OFFSET
PHASE
RESET
TRANSLATOR
FREQUENCY
CLK
A/B
COMPLEX
16
3
NCO
INPUT
DATA
TIMING
Q
SYNC
I
I/O
18
18
3
SCALING
EXPLNV,
EXPOFF
EXP
f
TRST
SAMP
FIXED OR WITH EXPONENT
REAL, DUAL, COMPLEX
TCK TMS
INPUT MODE
NCO FREQUENCY
SCALING
PHASE OFFSET
SYNC M/S
SYNC MASK
JTAG
CIC2
DITHER
INTERLEAVE
TDI TDO
M
CICS
DECIMATE FACTORS
SCALE FACTORS
D[7:0] A[2:0]
CIC2, CIC5
MICROPROCESSOR INTERFACE
PLEXER
MULTI-
CONTROL REGISTERS
MICROPORT AND
SERIAL ACCESS
f
SAMP2
CS
(W/R)
RCF COEFFICIENTS
DECIMATE FACTOR
NUMBER OF TAPS
ADDRESS OFFSET
R/W
SCALING
(R/D)
DS
ARCHITECTURE
As shown in Figure 1, the AD6620 has four main signal pro-
cessing stages: a Frequency Translator, two Cascaded Integrator
Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR
Filter (RCF). Multiple modes are supported for clocking data
into and out of the chip. Programming and control is accom-
plished via serial and microprocessor interfaces.
Input data to the chip may be real or complex. If the input data
is real, it may be clocked in as a single channel or interleaved
with a second channel. The two-channel input mode, called
Diversity Channel Real, is typically used in diversity receiver
applications. Input data is clocked in 16-bit parallel words,
IN[15:0]. This word may be combined with exponent input bits
EXP[2:0] when the AD6620 is being driven by floating-point or
gain-ranging analog-to-digital converters such as the AD6600.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into in-phase (I) and quadrature (Q)
components. This stage translates the input signal from a digital
intermediate frequency (IF) to baseband. Phase and amplitude
dither may be enabled on-chip to improve spurious performance
of the NCO. A phase offset word is available to create a known
phase relationship between multiple AD6620s.
Following frequency translation is a fixed coefficient, high speed
decimating filter that reduces the sample rate by a program-
mable ratio between 2 and 16. This is a second order, cascaded
integrator comb FIR filter shown as CIC2 in Figure 1. (Note:
Decimation of 1 in CIC2 requires 2× or greater clock into
AD6620). The data rate into this stage equals the input data
rate, f
the decimation factor, M
CIC5
DTACK
(RDY)
OUTPUT
FACTOR
SCALE
M
SAMP
CICS
. The data rate out of CIC2, f
MODE PAR/SER
PLEXER
f
MULTI-
SAMP5
SCALING, S
PARALLEL
23
16
CIC2
INTERLEAVE
OUT
OUTPUT
.
DE-
23
MULTIPLEXER
SERIAL
256
256
256
C-RAM
Q-RAM
I-RAM
SAMP2
PARALLEL
SERIAL I/O
OUTPUTS
RCF
18
20
18
AND
, is determined by
A/B
DV
I/Q
OUT
OUT
M
OUT
16
RCF
OUT[15:0]
SCLK
SDI
SDO
SDFS
SDFE
SBM
WL[1:0]
AD
SDIV[3:0]