AD6620S/PCB Analog Devices Inc, AD6620S/PCB Datasheet - Page 39

• Manufacturer Part Number: AD6620S/PCB
• Description: BOARD EVAL DUAL RCVR W/AD6620AS
• Manufacturer: Analog Devices Inc

Specifications of AD6620S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6620

the SDO of the master AD6620 takes control of the SDO line
and begins shifting data out of the device. When all data has
been shifted, the master raises the SDFE on the last shifted.
This signals the next chip (slave) that on the next cycle of the
clock it should take control of the SDO line and begin shifting
data to the DSP. When the second AD6620 completes its shift,
it raises its SDFE to signal the next chip in the chain, if present.
If additional devices are connected to the chain, this would be
used to indicate they should take control on the next clock cycle.
This application does not have a third device and therefore, the
frame would end.
Normally in an application with a single AD6620, the AD6620
would be configured as the serial bus master. However, there
are applications where the DSP or other device may be the serial
bus master. In this case, the diagram below illustrates how to
configure the AD6620 so that it may be used in this mode. In
order to use this in a meaningful application, the DSP must
know when the AD6620 has new data available on its output. If
the DSP polls the AD6620 too early, either old data will be present
or the data could be in an indeterminate state. To prevent this,
the AD6620 has an output pin DV
when new data is available. This should be tied to an interrupt
line of the DSP that is edge-sensitive, as the DV
valid for two or four high speed clock cycles depending on the
mode of the chip. The DSP may then invoke an interrupt service
routine to handle the data, see text below. In this application,
the DSP is responsible for generating the framing and clocking
signals to the AD6620 as shown in Figure 51.
CASCADE
AD6620
2
2
2
AD6620
AD6620
WL
WL
SBM
WL
+3.3V
SBM
SBM
AD
AD
AD
DV
4
4
4
SDIV
SDIV
SDIV
SCLK
SDFS
SDFE
SCLK
SDFS
SDFE
SCLK
OUT
SDFS
SDFE
SDO
SDO
SDO
SDI
SDI
SDI
10k
OUT
10k
that signals the DSP
SCLK
DT
DR
RFS
10k
SCLK
DT
DR
RFS
IRQ
OUT
DSP
DSP
10k
line is only
Software for Single Channel Real Operation
When interfacing Analog Device’s SHARC DSP, the following
code fragments can be used to configure the SHARC. The first
example shows how to configure the registers for use with a single
channel application. The first segment of code defines the memory
for use with the multichannel serial port data. The second segment
of code sets up the serial port for receiving data only. It could
have just as easily been set up for bidirectional data by properly
setting the MTCSI register. The final two code segments are used
when a serial port interrupt occurs. When the SHARC detects
completion of the serial port frame, an interrupt is generated
and the final code segment is executed. The comments in that
section show where user code should be inserted. The SHARC
takes care of moving the serial port buffers data directly to data
memory as shown.
/ ————————————————————————————— /
/ multi-channel register setup /
.SEGMENT/DM dm_data;
.VAR fm_demod_data[2];
sample /
.VAR fm_demod_tcb[8] = 0, 0, 0, 0, fm_demod_data+7, 2, 1,
fm_demod_data;
/ ————————————————————————————— /
/ ————————————————————————————— /
/ Subroutine to setup sport1 for use with the AD6620 /
setup_sport1:
/ ————————————————————————————— /
spr1_svc:
/ ————————————————————————————— /
/ ————————————————————————————— /
/ Process received data here. Data samples located in fm_demod_data
and fm_demod_data+1
spr1_asserted:
r0 = 0;
dm(MTCS1) = r0;
r0 = 0;
dm(MTCCS1) = r0;
dm(MRCCS1) = r0;
r0 = 0x00100000;
dm(STCTL1) = r0;
r0 = 0x038c20f2;
dm(SRCTL1) = r0;
r0 = fm_demod_tcb + 7; / TCB address /
dm(CP1) = r0;
rts (db);
bit set imask SPR1I;
nop;
RTI;
RTI;
RTI;
push sts;
/ Use secondary set of DAGs and Register file /
/ Transfer Control Block for reception of fm data /
/ multi-channel enable setup /
/ do not transmit on any channels /
/ Compand Setup /
/ no companding on transmit /
/ no companding on receive /
/ Setup sport 1 transmit control register /
/ mfd = 1 /
/ Setup sport 1 receive control register /
/ slen = 15, sden & schen enabled /
/ sign extend, external SCLK+RFS /
/ Kickoff DMA chain /
/ RETURN /
/ enable sport1 receive interrupt /
jump spr1_asserted;
/ Push the status stack /
/ Array for receiving 1 real and imag
AD6620