MGA-68563-BLKG Avago Technologies US Inc., MGA-68563-BLKG Datasheet - Page 3

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MGA-68563-BLKG

Manufacturer Part Number
MGA-68563-BLKG
Description
IC AMP LNA MMIC GAAS SMD SOT-363
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of MGA-68563-BLKG

Gain
19.7dB
Current - Supply
16mA
Frequency
100MHz ~ 1.5GHz
Noise Figure
1dB
P1db
17.5dBm
Package / Case
SC-70-6, SC-88, SOT-363
Test Frequency
500MHz
Voltage - Supply
3V
Frequency Range
0.1GHz To 1.5GHz
Noise Figure Typ
1dB
Power Dissipation Pd
600mW
Supply Current
11mA
Rf Type
DAB, DVB-H, DVB-T, ISDB-T, Media-FLO, T-DMB
Manufacturer's Type
Low Noise Amplifier
Number Of Channels
1
Frequency (max)
1.5GHz
Operating Supply Voltage (typ)
3V
Package Type
SOT-363
Mounting
Surface Mount
Pin Count
6
Noise Figure (typ)
1@500MHzdB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
516-2129

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MGA-68563-BLKG
Manufacturer:
AVAGO
Quantity:
67 000
Part Number:
MGA-68563-BLKG
Manufacturer:
AVAGO/安华高
Quantity:
20 000
MGA-68563 Electrical Specifications
T
Symbol
Id
NF
G
OIP3
P1dB
Notes:
1. Guaranteed specifications are 100% tested in the production test circuit, the typical value is based on measurement of at least 600 parts from
2. Circuit achieved a trade-off between optimal NF, Gain, OIP3 and input return loss.
Figure 2. Id @ 3V.LSL=7, Nominal=11, USL=16
Figure 4. NF @ 0.5GHz 3V.USL=1.4, Nominal=1.0
Note:
Measured on the production circuit.
Distribution data sample size is 600 samples taken from 2 non-consecutive wafer lots. Future wafers allocated to this product may have nominal
values anywhere between upper and lower limits.
3
.7
6 7 8 9 10 11 12 13 14 15 16 17
C
test [1,2]
CPK=1.62
[1,2]
test
= 25qC, Z
two non-consecutive wafer lots during initial characterization of this product.
LSL
test
test [1,2]
.8
[1,2]
CPK=2.13
[1,2]
.9
O
Parameters and Test Conditions
Device Current
Noise Figure in test circuit
Associated Gain in test circuit
Output 3
Output Power at 1dB Gain Compression in test circuit.
= 50:, V
1
1.1 1.2 1.3 1.4 1.5
rd
d
Order Intercept in test circuit
= 3V (unless otherwise specified)
USL
USL
[1]
[1]
[1]
Figure 3, OIP3 @ 0.5GHz 3V. LSL=18, Nominal=20.7
Figure 5. Gain @ 0.5GHz 3V.USL=18, Nominal=19.7, USL=21.5
18
18 18.5 19 19.5 20 20.5 21 21.5 22
LSL
LSL
[1]
Freq
f = 0.5 GHz
f = 0.5 GHz
f = 0.5 GHz
CPK=3.228
CPK=2.276
19
Units
mA
dB
dB
dBm
f = 0.5 GHz
20
Min.
18
18
21
Typ.
11
1.0
19.7
20.7
dBm
USL
22
Max.
16
1.4
21.5
17.5

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