EM250-RCM-R Ember, EM250-RCM-R Datasheet - Page 65

• Manufacturer Part Number: EM250-RCM-R
• Description: EM250 RCM BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4/ZigBeer

Specifications of EM250-RCM-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1023

Receiving a character always causes a serialization of a transmit character pulled from the transmit FIFO.
When the transmit FIFO is empty, a transmit underrun is detected (no data in transmit FIFO) and the register
bit
the SPI serializer retransmits the last transmitted character or a busy token (
the register bit
Note: Even during a transmit underrun, the register bit
When a transmit character is written to the (empty) transmit FIFO, the
INT_SC2FLAG
is full, which causes the register bit
ter begins to clock data out of the MISO pin, the register bit
clears (after the first bit is clocked out) and indicates that not all characters are transmitted yet. After shift-
ing one full transmit character to the MISO pin, space for one transmit character becomes available in the
transmit FIFO. This causes the register bit
characters are shifted out, the transmit FIFO is empty, which causes the register bit
SC2_SPISTAT
The SPI slave controller must guarantee that there is time to move new transmit data from the transmit FIFO
into the hardware serializer. To provide sufficient time, the SPI slave controller inserts a byte of padding,
0xFF, onto the start of transmit data. This byte of padding is only inserted when slave select is deasserted,
the FIFO is empty, and the transmitter (serializer) is idle. An idle transmitter is indicated by the
SC_SPITXIDLE
do not include a byte of padding. But, if any new data is written to the transmit FIFO while slave select is
deasserted, the first byte immediately goes into the transmit serializer without waiting for clocks from the
external SPI master. The transmit serializer will still hold this data until there are clocks from the master.
Because the data goes directly into the serializer, there is a race condition between when the data enters the
serializer and when the SPI master attempts to clock out the data. If the data enters the serializer after the
SPI master begins clocking data, then a byte of padding is transmitted as described above. If the data enters
the serializer before the SPI master begins clocking data, then the first byte of data is transmitted without a
byte of padding. Because of this race condition and the inability of the SPI master to know the current,
internal state of the EM250, it is best to design a protocol around SPI slave interaction that handles this race
condition and avoids potential issues. Some possible protocol solutions are:
Interrupts are generated by one of the following events:
INT_SCTXUND
SPI slave does not place data into the transmit FIFO until the SPI status indicates that the SPI master has
begun clocking data. One possible indication of this is the
The communications between the SPI master and SPI slave use an interrogation-response scheme where
the SPI slave only queues up data for transmission after receiving data from the master, without slave se-
lect deasserting between the two events.
SPI slave begins all transmissions with its own byte of padding, such that the master always receives one
or two bytes of padding.
The data from SPI slave includes a data integrity scheme where the information received by the master
can be validated as accurate.
Transmit FIFO empty and last character shifted out (0 to 1 transition of
Transmit FIFO changed from full to not full (0 to 1 transition of
Receive FIFO changed from empty to not empty (0 to 1 transition of
Transmit DMA buffer A/B complete (1 to 0 transition of
Receive DMA buffer A/B complete (1 to 0 transition of
Received and lost character while receive FIFO was full (Receive overrun error)
clear when the SPI master begins to clock data out of the MISO pin, indicating the transmitter is not
idle. After a complete byte has been clocked out, the bit
bit
INT_SCTXIDLE
INT_SCTXIDLE
register do not change. Further transmit characters can be written to the transmit FIFO until it
register to be set.
SC_SPIRPT
bit in the
in the
will toggle in this manner for every byte that is transmitted as an underrun.
INT_SC2FLAG
SC2_SPISTAT
in the
in the
INT_SC2FLAG
SC2_SPICFG
SC_SPITXFREE
register is set. Because there is no character available for serialization,
register. Subsequent transmissions while slave select remains asserted
SC_SPITXFREE
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register.
interrupt register will be set. The bits
in the
SC_SPITXIDLE
in the
SC2_SPISTAT
SC_RXACTA/B
SC_TXACTA/B
SC_SPITXIDLE
SC_SPIRXVAL
SC2_SPISTAT
SC_SPITXIDLE
SC_SPITXFREE
SC2_SPISTAT
)
SC_SPIRXVAL
in the
register to clear. When the SPI mas-
)
SC_SPITXIDLE
in the
0xFF
bit.
register to be set. After all
SC2_SPISTAT
will be set and the register
), which is determined by
SC2_SPISTAT
)
SC_SPITXIDLE
register and the
SC_SPITXIDLE
)
)
register will
EM250
register
120-0082-000S
in the
and