EM250-RCM-R Ember, EM250-RCM-R Datasheet - Page 98

• Manufacturer Part Number: EM250-RCM-R
• Description: EM250 RCM BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4/ZigBeer

Specifications of EM250-RCM-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1023

EM250
120-0082-000S
The conversion rate is programmed by setting the
the ADC can be chosen from various sources and is configured with the
As described in Table 34, the ADC inputs can be single-ended (routed individually to ADC0, ADC1, ADC2, or
ADC3) or differential (routed to pairs ADC0-ADC1 and ADC2-ADC3). For selecting alternate pin functions, refer
to Table 17 and Table 18.
Setting the
will continually generate conversions until the
INT_ADC
enabled in the
completes. After each
the next conversion.
To ensure the pipelined digital filter in the ADC is flushed,
to
The ADC uses an internal reference, VREF, which may be routed out to the alternate pin function of GPIO8,
VREF_OUT. VREF_OUT is only enabled when the
close to 1.2V as possible by the EmberZNet software, using the regulated supply (VDD) as reference. VREF is
able to source modest current (see Table 36) and is stable under capacitive loads. The ADC cannot accept an
external VREF input. For selecting alternate pin functions, refer to Table 17 and Table 18.
While the ADC Module supports both single-ended and differential inputs, the ADC input stage is differential.
Single-ended operation is provided by internally connecting one of the differential inputs to VREF/2 while fully
differential operation uses two external signals. The full-scale differential input range spans -VREF to +VREF
and the single-ended input range spans 0 to VREF.
Sampling of internal connections VSS and VREF allow for offset and gain calibration of the ADC in applications
where absolute accuracy is important. Measurement of the unregulated supply VDD_PADS, 2.1-3.6V pad sup-
ply, allows battery voltage to be monitored. Measurement of the regulated supply VDD, 1.8V core supply, pro-
vides an accurate means of calibrating the ADC as the regulator is factory trimmed to 1.72V.
Offset and gain correction using VREF or VDD reduces both ADC gain errors and reference errors but it is lim-
ited by the absolute accuracy of the supply. Correction using VREF is recommended because VREF is calibrated
by the EmberZNet software against VDD, which is factory trimmed to 1.72V. Table 35 shows the equations
used.
ADC_SEL[3:0]
ADC_SEL
10
0
1
2
3
4
5
6
7
8
9
interrupt is generated. In order for this to interrupt the CPU the interrupt mask
ADC_EN
or
ADC_RATE
INT_CFG
Analog Source of ADC
ADC0
ADC1
ADC2
ADC3
(1/4) * VDD_PADS (2.1–3.6V pad supply)
(1/2) * VDD (1.8V core supply)
RESERVED
VSS (0V)
VREF
ADC0–ADC1
ADC2–ADC3
bit in the
INT_ADC
register. The
. Discard the first sample after
ADC_CFG
interrupt, the
INT_ADC
register will cause the ADC to immediately begin conversions. The ADC
Table 34. ADC Inputs
Page 98
INT_ADC
ADC_EN
interrupt is the only means for determining when a conversion
ADC_EN
ADC_RATE
bit is cleared. When each conversion completes, an
interrupt bit must be cleared to detect completion of
ADC_EN
bit in the
ADC_EN
bits in the
is set.
ADC_CFG
GPIO Pin
should be cleared before changes are made
4–5
6–7
ADC_SEL
4
5
6
7
8
ADC_CFG
register is set. VREF is trimmed as
bits in the
Purpose
Single-ended
Single-ended
Single-ended
Single-ended
Supply monitoring
Supply monitoring
Calibration
Calibration
Differential
Differential
register. The analog input of
INT_ADC
ADC_CFG
must be
register.