EM35X-DEV-IAR Ember, EM35X-DEV-IAR Datasheet - Page 125
EM35X-DEV-IAR
Manufacturer Part Number
EM35X-DEV-IAR
Description
KIT DEV EM35X IAR EWARM ZIGBEE
Manufacturer
Ember
Series
EM35xr
Type
Zigbeer
Specifications of EM35X-DEV-IAR
Frequency
2.4GHz
For Use With/related Products
EM351, EM357
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1027
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9 General Purpose Timers (TIM1 and TIM2)
9.1 Introduction
Each of the EM35x’s two general-purpose timers consists of a 16-bit auto-reload counter driven by a
programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of
input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and
waveform periods can be modulated from a few microseconds to several milliseconds using the timer
prescaler. The timers are completely independent, and do not share any resources. They can be synchronized
together as described in the Timer Synchronization section.
The two general-purpose timers, TIM1 and TIM2, have the following features:
Figure 9-1 shows an overview of a timer’s internal structure.
Note: Because the two timers are identical, the notation TIMx refers to either TIM1 or TIM2. For example,
TIMx_PSC refers to both TIM1_PSC and TIM2_PSC. Similarly, “y” refers to any of the four channels of a given
timer, so for example, OCy refers to OC1, OC2, OC3, and OC4.
16-bit up, down, or up/down auto-reload counter.
Programmable prescaler to divide the counter clock by any power of two from 1 through 32768.
4 independent channels for:
Synchronization circuit to control the timer with external signals and to interconnect the timers.
Flexible clock source selection:
Interrupt generation on the following events:
Supports incremental (quadrature) encoders and Hall sensors for positioning applications.
Trigger input for external clock or cycle-by-cycle current management.
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•
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•
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Input capture
Output compare
PWM generation (edge- and center-aligned mode)
One-pulse mode output
Peripheral clock (PCLK at 6 or 12 MHz)
32.768 kHz external clock (if available)
1 kHz clock
GPIO input
Update: counter overflow/underflow, counter initialization (software or internal/external trigger)
Trigger event (counter start, stop, initialization or count by internal/external trigger)
Input capture
Output compare
Final
9-1
120-035X-000G
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