MPC8377EWLANA Freescale Semiconductor, MPC8377EWLANA Datasheet - Page 68

• Manufacturer Part Number: MPC8377EWLANA
• Description: ACCESS POINT/ROUTER MPC8377
• Manufacturer: Freescale Semiconductor

Specifications of MPC8377EWLANA

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express
parasitic characteristics that cause the real PCI Express component to vary in impedance from the
compliance/test measurement load. The input receiver eye diagram is implementation specific and is not
specified. Rx component designer should provide additional margin to adequately compensate for the
degraded minimum receiver eye diagram (shown in
adequate combination of system simulations and the return loss measured looking into the Rx package and
silicon. The Rx eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
68
Figure 43. Minimum Receiver Eye Timing and Voltage Compliance Specification
The reference impedance for return loss measurements is 50 Ω to ground for
both the D+ and D– line (that is, as measured by a Vector Network Analyzer
with 50 Ω probes—see
C
PEACCTX
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
(D+ D– Crossing Point)
V
RX-DIFF
, are optional for the return loss measurement.
= 0 mV
Figure
V
RX-DIFFp-p-MIN
0.4 UI = T
44). Note that the series capacitors,
NOTE
RX-EYE-MIN
Figure
> 175 mV
43) expected at the input receiver based on an
(D+ D– Crossing Point)
V
RX-DIFF
= 0 mV
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