AT86RF211SDK E2V, AT86RF211SDK Datasheet - Page 36
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AT86RF211SDK
Manufacturer Part Number
AT86RF211SDK
Description
KIT DEV FOR AT86RF211/915MHZ
Manufacturer
E2V
Series
Smart RFr
Type
Transceiverr
Datasheet
1.AT86RF211SDK.pdf
(66 pages)
Specifications of AT86RF211SDK
Frequency
915MHz
For Use With/related Products
AT86RF211 @ 915MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT86RF211-DK
AT86RF211-DK915107
AT86RF211DK
AT86RF211DK915107
AT86RF211DK915107
AT86RF211-DK915107
AT86RF211DK
AT86RF211DK915107
AT86RF211DK915107
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2.5.1.3
Figure 2-30. Read Chronogram: Complete Read Cycle from a 10-bit Register
36
AT86RF211S
SLE
SCK
SDATA
SDATA
Direction
READ Mode (R/W = 0)
A[3]
A[2 ]
INPUT
The address and R/W bits are clocked on the rising edge of SCK and the data bits are
changed on the falling edge of SCK. The register’s MSB is the first bit read.
The SDATA I/O pin is switched from input to output on the edge following the 1 clocking
the R/W bit.
It is possible to stop reading a register (by reverting SLE to 1) at any time.
If an attempt is detected to read more bits than the register capacity, SDATA is clamped
to 0.
If the address of a register is not valid, SDATA is set to 1 during the first 32 SCK periods,
and then to 0 during all the extra periods.
SDATA is switched back to the input state when SLE reverts to 1.
Figure 2-31. Read Chronogram: Partial Read Cycle, Reading 2 Bits
A[1]
A[0]
R/W
SLE
SCK
SDATA
SDATA
Mode
D[9 ]
D[8]
D[7]
A[3]
D[6]
A[2]
INPUT
D[5]
OUTPUT
A[1]
D[4]
A[0]
D[3]
R/W
D[2]
D[31]
OUTPUT
D[1]
D[30]
D[0]
INPUT
INPUT
5348B–WIRE–03/06
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