PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet
PCX107AVZFU100LC
Specifications of PCX107AVZFU100LC
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PCX107AVZFU100LC Summary of contents
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Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM • Compliant with PCI Specification, Revision 2.1 • ...
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Screening This product is manufactured in full compliance with: • HiTCE CBGA according to Atmel standards • PBGA upscreening based upon Atmel standards • Full military temperature range (Tj = -55°C, +125°C) • Industrial temperature range (Tj = -40°C, +110°C) ...
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General Parameters The following list provides a summary of the general parameters of the PC107A: Technology Die size Transistor count Logic design Package Core power supply I/O power supply 1.2 Features The PC107A provides an integrated high-bandwidth, high-performance interface ...
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PCI agent mode capability – Address translation unit – Some internal configuration registers accessible from PCI • Two-channel Integrated DMA Controller (Writes to ROM/Port × Not Supported) – Supports direct mode or chaining mode (automatic linking of DMA transfers) ...
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Pin Assignments 2.1 Pinout Listings Table 2-1 Table 2-1. PC107A Pinout Listing Signal Name Package Pin Number AE22, AE16, AA14, AE17, AD21, AD14, AD20, AB16, AB20, AB15, AA20, AD13, Y15, AE12, AD15, AB9, A[0–31] AB14, AA8, AC13, Y12, Y11, ...
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Table 2-1. PC107A Pinout Listing (Continued) Signal Name Package Pin Number WT AC16 N23, N21, M20, M21, M22, M24, M25, L20, L22, K25, K24, K23, K21, J20, AD[31–0] J24, J25, H20, F24, E25, F21, E24, E22, D25, A25, B25, A23, ...
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Table 2-1. PC107A Pinout Listing (Continued) Signal Name Package Pin Number RCS3 D7 SDBA0 A9 SDBA1 A8 SDCAS D4 E10, F9, D9, F8, E8, D8, B8, E7, C7, SDMA[13–0] B7, A7, B6, A6, A5 SDRAS INT Y22 ...
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Table 2-1. PC107A Pinout Listing (Continued) Signal Name Package Pin Number PLL_CFG[0–3] AC22, AD23, AD22, AE23 TCK W24 TDI Y25 TDO W23 TEST AA25 TEST1 V24 TEST2 D6 TMS Y24 TRIG_IN W22 TRIG_OUT W21 TRST AA24 AV AE24 DD AA21, ...
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Notes: 1. This pin has an internal pull-up resistor which is enabled only when the PC107A is in the reset state. The value of the inter- nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic ...
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Signal Description Figure 3-1. PC107A Microprocessor Signal Groups Memory Interface Signals EPIC Control Signals Two-wire Interface Control Signals Clock Signals Miscellaneous Signals Power and Ground Signals PC107A 10 A[0-31 CAS/DQM[0-7] AACK 8 1 ARTRY CKE 1 1 ...
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Detailed Specification This specification describes the specific requirements for the PC107A, in compliance with Atmel standard screening. 5. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics. 2. SQ32S0100.0: Quality levels for supplied components. The microcircuits are in ...
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Recommended Operating Conditions Table 5-2 Table 5-2. Recommended Operating Conditions Symbol Characteristic V Supply Voltage DD GV Supply Voltages for Memory Bus Drivers DD BV Supply Voltages for Processor Bus Drivers DD OV I/O Buffer supply for PCI and ...
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Figure 5-1 shows the supply voltage sequencing and separation cautions. Figure 5-1. Supply Voltage Sequencing and Separation Cautions 5V 3.3V 6 2.5V 0 Voltage Regulator Delay (2) Reset Configuration Pins HRESET HRESET_CPU Notes: 2137D–HIREL–08/05 8 See Note 1 below. 9 ...
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Figure 5-2 Figure 5-2. Figure 5-3 and 5V signals, respectively. Figure 5-3. PC107A 14 shows the undershoot and overshoot voltage of the memory interface of the PC107A. Overshoot/Undershoot Voltage 4V GVdd +5% GVdd VIH Gnd Gnd - 0.3V VIL Gnd ...
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Figure 5-4. 6. Thermal Information 6.1 Package Characteristics Table 6-1 Table 6-1. Symbol Rθ JA Rθ JMA Rθ JMA Rθ JMA Rθ JB Rθ JC Note: 2137D–HIREL–08/05 Maximum AC Waveforms for 3.3V Signaling 11 ns (Min) Overvoltage Waveform (Max) Undervoltage ...
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Package Thermal Characteristics for HiTCE Table 6-2 Table 6-2. Package Thermal Characteristics for HiTCE Package Characteristic (2) Thermal resistance junction to case Thermal resistance junction to bottom of balls Thermal resistance junction to board, Jedec JESD51-8 (2s2p board) Thermal ...
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Thermal Management Information An estimation of the chip junction temperature where T = ambient temperature for the package (° junction-to-ambient thermal resistance (°C/W) θ power dissipation in the ...
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Figure 6-1. The board designer can choose between several types of heat sinks to place on the PC107. There are several commercially available heat sinks for the PC107 provided by the listvendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 ...
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Internal Package Conduction Resistance For the PBGA packaging technology, the intrinsic conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance, • The die junction-to-ball thermal resistance. Figure 6-2 mounted to a printed-circuit board. Figure 6-2. ...
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Power Characteristics Table 6-3 sumption on the PLL supply pin (AV information is based on characterization data. Table 6-3. Power Consumption 25/50 V I/O DD Mode Power Power Typical 468 923 Doze 176 697 Nap 139 744 Sleep 79 ...
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Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the PC107A. 7.1 Static Characteristics 7.1.1 DC Electrical Specification Table 7-1 conditions (see Table 7-1. DC Electrical Specifications Characteristics (2)(3) Input High Voltage Input ...
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Output Driver Characteristics Table 7 page http://www.freescale.com/semiconductor. Table 7-2. Drive Capability of PC107A Output Pins Programmable Output Driver Type Impedance (Ohms) 20 DRV_CPU 40 (default) 25 DRV_PCI 50 (default) 8 (default) ...
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Dynamic Electrical Characteristics 7.2.1 Clock AC Specifications Table 7-3 At recommended operating conditions (see LV = 3.3 DD Table 7-3. Clock AC Timing Specifications Num Characteristics and Conditions 1a Frequency of Operation (PCI_SYNC_IN) 1b PCI_SYNC_IN Cycle Time 2, 3 ...
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Figure 7-1 Table 7-3 ating Frequency” on page 25 Operation. Figure 7-1. PCI_SYNC-IN Input Clock Timing Diagram PCI_SYNC_IN Figure 7-2. Clock Subsystem Block Diagram MPC107 OSC_IN Specs Note: PC107A 24 shows the PCI_SYNC_IN Input Clock Timing Diagram, ...
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Figure 7-3. DLL Locking Range Loop Delay (DLL_Standard = clk = 1 loop + 27 Figure 7-4. DLL Locking Range Loop Delay (DLL_Standard ...
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At recommended operating conditions (see Table 7-4. Characteristic Core (memory bus/processor bus) frequency PCI input frequency (PCI_SYNC_IN) Note: PC107A 26 Operating Frequency (1) 1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0–3] settings must be chosen such that the resulting peripheral logic/memory ...
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Input AC Timing Specifications Table 7-5 on page At recommended operating conditions (see LV = 3.3 DD Table 7-5. Input AC Timing Specifications Num Characteristics PCI Input Signals 10a Valid to PCI_SYNC_IN (Input Setup) Memory Interface Signals 10b Valid ...
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Figure 7-5. Input – Output Timing Diagram Referenced to SDRAM_SYNC_IN PCI_SYNC_IN SDRAM_SYNC_IN shown in 2:1 mode MEMORY INPUTS/OUTPUTS Figure 7-6. Input – Output Timing Diagram Referenced to PCI_SYNC_IN PCI_SYNC_IN PCI INPUTS/OUTPUTS Figure 7-7. Input Timing Diagram for Mode Select Signals ...
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Output AC Timing Specification Table 7-6 on page 28 At recommended operating conditions (see Table 7-6. Output AC Timing Specifications (3)(6) Num Characteristics PCI_SYNC_IN to Output Valid, 66 MHz PCI, with SDMA4 pulled- down to logic 0 state. See ...
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PCI Signal Output Hold Timing In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz and 66 MHz PCI systems, the PC107A has a programmable output hold delay for PCI signals. The initial value ...
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Figure 7-9. PCI_HOLD_DEL Effect on Output Valid and Hold Time PCI_SYNC_IN 12a for 33 MHz PCI PCI_HOLD_DEL = 100 PCI INPUTS/OUTPUTS 33 MHz PCI 12a for 66 MHz PCI PCI_HOLD_DEL = 000 PCI INPUTS/OUTPUTS 66 MHz ...
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Two-wire Interface AC Timing Specifications Table 7-8 At recommended operating conditions (see Table 7-8. Two-wire Interface Input AC Timing Specifications Num Characteristics 1 Start condition hold time Clock low period (The time before the PC107A will drive SCL low ...
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Table 7-9 PC107A. At recommended operating conditions (see Table 7-9. PC8240 Maximum (2) FDR Hex 20, 21 22, 23, 24, 25 224, 256, 320, 384 0, 1 384, 448, 480, 512, 640 26, 27, 28 ...
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Table 7-10 At recommended operating conditions (see LV = 3.3 DD Table 7-10. Output AC Timing Specifications Two-wire Interface Num Characteristics 1 Start condition hold time 2 Clock low period 3 SCL/SDA rise time (from 0.5V to 2.4V) 4 Data ...
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Figure 7-11. Timing Diagram II Two-wire Interface VM SCL 8 SDA Figure 7-12. Timing Diagram III Two-wire Interface DFFSR FILTER CLK (1) SDA Note: Figure 7-13. Timing Diagram IV (Qualified Signal) Two-wire Interface VM SCL/SDArealtime Delay (1) SCL/SDAqualified Note: 2137D–HIREL–08/05 ...
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EPIC Serial Interrupt Mode AC Timing Specifications Table 7-11 At recommended operating conditions (see Table 7-11. EPIC Serial Interrupt Mode AC Timing Specifications Num Characteristics 1 S_CLK Frequency 2 S_CLK Duty Cycle 3 S_CLK Output Valid Time 4 Output ...
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IEEE 1149.1 (JTAG) AC Timing Specifications Table 7-12 ating mode. At recommended operating conditions (see Table 7-12. Num Notes: Figure 7-16. JTAG Clock Input Timing Diagram ...
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Figure 7-18. JTAG Boundary Scan Timing Diagram TCK DATA INPUTS DATA OUTPUTS DATA OUTPUTS Figure 7-19. Test Access Port Timing Diagram TCK TDI, TMS TDO TDO PC107A INPUT DATA VALID 8 OUTPUT DATA VALID ...
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Preparation for Delivery 8.1 Packaging Microcircuits are prepared for delivery in accordance with internal standards. 8.2 Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with internal ...
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Notes: 1. PLL_CFG[0–3] settings not listed (00000100, 0110, 0111, 1010, 1011, and 1110) are reserved PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal core directly, the PLL is disabled, and the PCI: core mode is set ...
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Mechanical Dimensions Figure 9-1 Figure 9-1. PC107A Package Dimensions and Pinout Assignments 5 min A1 INDEX 14.5 Max 4 9 min ...
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Figure 9-2. Mechanical Dimensions and Bottom Surface Nomenclature of the 503-ball HiTCE CBGA Package BALL A1 INDEX 2X 0.2 - ...
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System Design Information 10.1 PLL Power Supply Filtering The AV eral logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL), respectively. To ensure stability of the internal clocks, the power supplied to the AV should be filtered of ...
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Figure 10-2. Example Voltage Sequencing Circuits + 5V Source 10.3 Decoupling Recommendations Due to the PC107A’s dynamic power management feature, large address and data buses, and high operating frequencies, the PC107A can generate transient power surges and high fre- quency ...
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Pull-up/Pull-down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The processor data bus signals are: DH[0 31], DL[0 – ...
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Definitions 11.1 Datasheet Status Description Table 11-1. Datasheet Status Datasheet Status Objective specification Target specification Preliminary specification α-site Preliminary specification β-site Product specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). ...
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Ordering Information Type Temperature Range -55˚C, +125˚C V: -40˚C, +110˚C Package (2) ZF: FC-PBGA Type (PCX107A if prototype) Temperature Range -55˚C, +125˚C V: -40˚C, +110˚C Package GH: HiTCE-CBGA Notes: 13. Document Revision History ...
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PC107A 48 2137D–HIREL–08/05 ...
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Table of Contents Features ..................................................................................................... 1 Description ................................................................................................ 1 Screening................................................................................................... 2 1 General Description ................................................................................. 2 2 Pin Assignments ...................................................................................... 5 3 Signal Description ................................................................................. 10 4 Detailed Specification ............................................................................ 11 5 Applicable Documents .......................................................................... 11 6 Thermal Information .............................................................................. ...
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Definitions .............................................................................................. 46 12 Ordering Information ............................................................................. 47 13 Document Revision History .................................................................. 47 PC107A ii 10.2 Power Supply Voltage Sequencing ......................................................................43 10.3 Decoupling Recommendations ............................................................................44 10.4 Connection Recommendations ............................................................................44 10.5 Pull-up/Pull-down Resistor Requirements ............................................................45 11.1 Datasheet Status Description ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...
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PC107A iv 2137D–HIREL–08/05 ...