MC44CC375AVEFEVK Freescale Semiconductor, MC44CC375AVEFEVK Datasheet - Page 4

• Manufacturer Part Number: MC44CC375AVEFEVK
• Description: CCEVK NEJA EVAL KIT
• Manufacturer: Freescale Semiconductor
• Type: Modulatorr

Specifications of MC44CC375AVEFEVK

• For Use With/related Products: MC44CC375AV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4151738; T0704786

VIDEO SECTION
ative going sync pulses and a nominal level of 1.0 V
signal is AC coupled to the video input where the sync tip lev-
el is clamped.
1.0 V
resistive divider at video input, resulting in a lower signal seen
by the video input stage.
whose function is to soft clip the top of the video waveform if
the amplitude from the sync tip to peak white goes too high.
In this way, over-modulation of the carrier by the video is
avoided. The clipping function is always engaged.
(100IRE = 0.7 V
SOUND SECTION
incorporating the sound subcarrier oscillator. The audio input
signal is AC coupled into the amplifier which then drives the
modulator.
external capacitor C1 and an internal resistor (100 kΩ typi-
cal). The recommended capacitor value (750 pF) is for NTSC
standards, time constant is 75 µs.
range, with pre-emphasis circuit engaged. Without this pre-
MC44CC375AV
4
The modulator requires a composite video input with neg-
The video modulation depth typical value is given for
The video signal is then passed to a peak white clip circuit
The clipping happens at 106IRE with 1.0 V
The PLL multivibrator oscillator is fully integrated.
The sound modulator system consists of an FM modulator
The audio pre-emphasis circuit is a high-pass filter with an
The audio bandwidth specification is for 50 Hz to 15 KHz
CBVS
input level. It can be reduced by simply adding a
pp
video blank to white).
pp
video signal
(pp)
. This
emphasis circuit, it is possible to extend the audio bandwidth
to high frequencies, as there is no internal frequency limita-
tion (stereo application, SAP, etc.).
PLL SECTION — DIVIDERS
ence frequency of 31.25 KHz with a 4.0 MHz crystal. The
31.25 KHz reference frequency is used for both the UHF and
Sound PLLs.
The VHF divider is also a fixed ÷8.
the CHS pin voltage in order to select channel 3 or channel 4.
PIN SELECTION
SOC is internally pulled up by 1.8 V. By default (open condi-
tion), all pins are “HI”.
Table 2. Configuration Pin Settings
*Please do not pull pin 3 to high voltage. For HI condition, leave pin
3 open.
Pin No
The reference divider is a fixed ÷128 resulting in a refer-
The prescaler is a fixed ÷8 and is permanently engaged.
The programmable divider’s division ratio is controlled by
Pins CHS and PSAVE are internally pulled up to 3.3 V,
16
1
3
Pin Name
PSAVE
CHS
SOC
Power Save Mode
CH3 - 61.25 MHz
LO (grounded)
Sound ON
Freescale Semiconductor
CH4 - 67.25 MHz
Normal Mode
Sound OFF
Digital Home
HI*