AD6624AABC Analog Devices Inc, AD6624AABC Datasheet - Page 26

• Manufacturer Part Number: AD6624AABC
• Description: IC RCVR SGNL PROC QUAD 196CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6624r

Specifications of AD6624AABC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

AD6624A
To configure a channel as a serial bus master, Bit 4 of register
0xA9 should be set high. However, as with the SDIV pins,
Channel 0 SBM is not mapped to memory and is instead pinned
out and must be hard-wired as either a master or a slave. Figure 34
shows the typical interconnections between an AD6624A Channel
in Serial Bus Master mode and a DSP.
Serial Slave Operation
The AD6624A can also be operated as a serial bus slave. In this
configuration, shown in Figure 35, the serial clock provided by the
DSP can be asynchronous with the AD6624A clock and input data.
In this mode, the clock has a maximum frequency of 62.5 MHz
and must be fast enough to read the entire serial frame prior to
the next frame coming available. Since the AD6624A output
is derived (via the Decimation/Interpolation Rates) from its
input sample rate, the output rate can be determined by the
user. The output rate of the AD6624A is given below.
f
OUT
=
M
AD6624A
CH 0
MASTER
AD6624A
CH 0
MASTER
AD6624A
CH 0
CASCADE
CIC
F
2
SBM0
SDIV0
3.3V
4
SBM0
ADC
×
SDIV0
3.3V
M
4
SCLK
SDFS
SDFE
×
CIC
SDO
SCLK
SCLK
SDFS
SDFE
SDFS
SDFE
SDI
SDO
SDO
L
SDI
SDI
5
CIC
×
10k
2
M
BUFFER
RCF
10k
SCLK
DT
DR
RFS
10k
SCLK
DT
DR
RFS
DSP
DSP
10k
(17)
Serial Ports Cascaded
Serial output ports may be cascaded on the AD6624A such that
the SDO’s outputs are shorted together. In this mode, the SDO
port of the master channel three-states when the SDO port of
the slave channel is active. This allows data to be shifted out of
a slave channel immediately following the completion of data
frame (I/Q pair) shifting out of a master AD6624A channel. To
accomplish this, the SDFE signal of the master channel drives
the SDFS input of the slave channel. Serial output port cascading
can be used with channels on the same AD6624A device, or
with channels on two different devices as shown in Figure 36.
To satisfy t
the SDFE signal from the master channel should be delayed
using a noninverting buffer (e.g., 74LVC244A) that provides a
minimum of 1.5 ns of propagation delay. Figure 36 shows the
cascade capability between two AD6624A devices. The first is
connected as a serial master (SBM = 1) and the second is
configured in Serial Cascade mode (SBM = 0).
Using the AD6624A master/slave mode permits a DSP to shift the
data from the master AD6624A serial port, followed immediately
by a frame of data (I and Q words) from the AD6624A slave port.
As shown in Figure 36, the master port is Serial Port 0. The slave
port can be either Serial Port 1, 2, or 3, or a Serial Port 0 from
another AD6624A. Other AD6624A serial ports can be cascaded
to the slave port by using the SDFE and SDFS in the manner
shown. The only limit to the number of ports that can be cascaded
comes from serial bandwidth and fan-out considerations.
There must be enough serial clock cycles available to shift the
necessary data into the DSP, and the SCLK (common to all
channels and DSP) must be closely monitored to ensure that it
is a clean signal. For systems where a single DSP serial port will
be connected to many AD6624A serial ports, it is recommended
that the SCLK signal from the master be buffered to the slaves.
See Serial Port Buffering in the Applications section.
SSF
AD6624A
CH 0
MASTER
AD6624A
CH 0
CASCADE
and t
SBM0
SDIV0
3.3V
HSF
4
SCLK
SCLK
timing requirements of the slave channel,
SDFS
SDFE
SDFS
SDFE
SDO
SDO
SDI
SDI
BUFFER
SCLK
DT
DR
RFS
10k
DSP
10k