AD6624AABC Analog Devices Inc, AD6624AABC Datasheet - Page 4

• Manufacturer Part Number: AD6624AABC
• Description: IC RCVR SGNL PROC QUAD 196CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6624r

Specifications of AD6624AABC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

AD6624A
GENERAL TIMING CHARACTERISTICS
Parameter (Conditions)
CLK Timing Requirements:
t
t
t
RESET Timing Requirement:
t
Input Wideband Data Timing Requirements:
t
t
Level Indicator Output Switching Characteristic:
t
SYNC Timing Requirements:
t
t
Serial Port Timing Requirements (SBM = 1):
Switching Characteristics:
t
t
t
t
t
t
t
t
t
Input Characteristics:
t
t
Serial Port Timing Requirements (SBM = 0):
Switching Characteristics:
t
t
t
t
t
t
Input Characteristics:
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
DSCLK1
All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
C
The timing parameters for SCLK, SDFS, SDFE, SDO, SDI, and DR apply to all four channels (0, 1, 2, and 3). The slave serial port’s (SCLK) operating frequency is
CLK
CLKL
CLKH
RESL
SI
HI
DLI
SS
HS
DSCLKH
DSCLKL
DSCLKLL
DSDFS
DSDFE
DSDO
DSDR
DDR
SSI
HSI
SCLK
SCLKL
SCLKH
DSDFE
DSDO
DSDR
SSF
HSF
SSI
HSI
limited to 62.5 MHz.
LOAD
= 40 pF on all outputs unless otherwise specified.
CLK Period
CLK Width Low
CLK Width High
RESET Width Low
Input to ↑CLK Setup Time
Input to ↑CLK Hold Time
↑CLK to LI (A–A, B; B–A, B) Output Delay Time
SYNC (A, B, C, D) to ↑CLK Setup Time
SYNC (A, B, C, D) to ↑CLK Hold Time
↑CLK to ↑SCLK Delay (Divide by 1)
↑CLK to ↑SCLK Delay (For Any Other Divisor)
↑CLK to ↓SCLK Delay (Divide by 2 or Even #)
↓CLK to ↓SCLK Delay (Divide by 3 or Odd #)
↑SCLK to SDFS Delay
↑SCLK to SDFE Delay
↑SCLK to SDO Delay
↑SCLK to DR Delay
↑CLK to DR Delay
SDI to ↓SCLK Setup Time
SDI to ↓SCLK Hold Time
SCLK Period
SCLK Low Time (When SDIV = 1, Divide by 1)
SCLK High Time (When SDIV = 1, Divide by 1)
↑SCLK to SDFE Delay
↑SCLK to SDO Delay
↑SCLK to DR Delay
SDFS to ↑SCLK Setup Time
SDFS to ↑SCLK Hold Time
SDI to ↓SCLK Setup Time
SDI to ↓SCLK Hold Time
3
3
1, 2
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
I
IV
IV
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
10
4.5
4.5
30.0
0.8
2.0
3.8
1.0
2.0
3.9
4.4
3.25
3.8
0.2
–0.4
–1.0
–0.3
5.4
2.4
3.0
16
5.0
5.0
3.8
3.7
3.9
1.9
0.7
2.4
2.0
Typ
0.5 × t
0.5 × t
AD6624AS
CLK
CLK
Max
12.6
13.4
14.0
6.7
6.9
5.3
+4.7
+4.0
+4.6
17.6
15.4
15.2
15.9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns