T5760-TGQ Atmel, T5760-TGQ Datasheet - Page 10

• Manufacturer Part Number: T5760-TGQ
• Description: IC RX 868MHZ ISM ASK/FSK 20-SOIC
• Manufacturer: Atmel

Specifications of T5760-TGQ

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: T5760-TGQTR

Figure 8. Polling Mode Flow Chart
Figure 9. Timing Diagram for Complete Successful Bit Check
10
IC_ACTIVE
( Number of checked Bits: 3 )
Bit check
Dem_out
Data_out (DATA)
T5760/T5761
NO
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
POLLING/_ON.
Output level on Pin IC_ACTIVE => high
I
S
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic is
enabled.
Output level on Pin IC_ACTIVE => low
I
Start-up mode:
The signal processing circuits are
enabled. After the start-up time (T
all circuits are in stable
condition and ready to receive.
Output level on Pin IC_ACTIVE => high
Bit-check mode:
The incomming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
Output level on Pin IC_ACTIVE => high
I
T
I
T
T
S
S
S
= I
Sleep
Startup
Bit-check
= I
= I
= I
Son
Soff
Son
Son
= Sleep x X
Start-up mode
T
Start-up
OFF command
Bit check
Sleep
OK ?
x 1024 x T
YES
Clk
Startup
1/2 Bit
)
1/2 Bit
Bit-check mode
T
Bit-check
Sleep:
X
T
T
1/2 Bit
T
Sleep
Startup
Bit-check
Clk
:
:
:
:
Bit check ok
1/2 Bit
Depends on the result of the bit check
If the bit check is ok, T
depends on the number of bits to be
checked (N
utilized data rate.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
defined by Baud0 and Baud1 in the
OPMODE register.
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleepStd
Basic clock cycle defined by fXTO
and Pin MODE
Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
according to Table 9
on T
Clk
1/2 Bit
. The baud-rate range is
Bit-check
1/2 Bit
) and on the
Bit-check
Receiving mode
4561B–RKE–10/02