T5760-TGQ Atmel, T5760-TGQ Datasheet - Page 11

• Manufacturer Part Number: T5760-TGQ
• Description: IC RX 868MHZ ISM ASK/FSK 20-SOIC
• Manufacturer: Atmel

Specifications of T5760-TGQ

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: T5760-TGQTR

Bit-check Mode
Configuring the Bit
Check
4561B–RKE–10/02
In bit-check mode the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subse-
quent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of this edge-to-edge
tests before the receiver switches to receiving mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to receiving mode due to noise. In the presence of a valid transmitter signal, the
bit check takes less time if N
time is not dependent on N
successfully and the data signal is transferred to Pin DATA.
According to Figure 10, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time t
the upper bit-check limit T
T
switches to sleep mode.
Figure 10. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between T
T
preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good
choice concerning that advice. A good compromise between receiver sensitivity and
susceptibility to noise is a time window of ± 30% regarding the expected edge-to-edge
time t
check limits must be programmed according to the required span.
The bit-check limits are determined by means of the formula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the
required T
T
to the chapter ‘Receiving Mode’. The lower limit should be set to Lim_min ³10. The max-
imum value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is <19, it is recommended to check 6 or 9 bits
(N
Lim_max
Lim_min
Lim_max
XClk
Lim_min
Bit-check
. The minimum edge-to-edge time t
ee
. Using pre-burst patterns that contain various edge-to-edge time periods, the bit-
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
= Lim_min ´ T
= (Lim_max -1) ´ T
or t
) to prevent switching to receiving mode due to noise.
Lim_min
Bit-check
ee
exceeds T
, T
in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge
Dem_out
Lim_max
XClk
Bit-check
and T
Lim_max
Bit-check
XClk
Lim_max
Bit-check
XClk
is set to a higher value, the receiver is less likely to
, the bit check will be terminated and the receiver
. Figure 9 shows an example where 3 bits are tested
, the check will be continued. If t
. The time resolution defining T
is set to a lower value. In polling mode, the bit-check
ee
T
Lim_min
T
Lim_max
is in between the lower bit-check limit T
t
ee
ee
(t
DATA_L_min
1/f
Sig
, t
DATA_H_min
T5760/T5761
) is defined according
Lim_min
ee
is smaller than
and T
Lim_min
Lim_min
Lim_max
and
and
11
is