TDA5212 Infineon Technologies, TDA5212 Datasheet - Page 18

• Manufacturer Part Number: TDA5212
• Description: IC FSK/ASK RECEIVER P-TSSOP-28
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5212

• Package / Case: 28-TSSOP
• Frequency: 902MHz ~ 928MHz
• Sensitivity: -109dBm
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Remote Control Systems
• Current - Receiving: 5.4mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 928 MHz
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Product Length (mm): 9.7mm
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Compliant
• Other names: TDA5212INTR

Wireless Components
3.4.1
3.4.2
3.4.3
3.4 Functional Blocks
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 902 to 928 MHz to the intermediate frequency (IF) at 10.7MHz with a
voltage gain of approximately 18 dB. A low pass filter with a corner frequency
of 20MHz is built on chip in order to suppress RF signals to appear at the IF out-
put ( IFO pin). The IF output is internally consisting of an emitter follower that
has a source impedance of approximately 330Ω to facilitate interfacing the pin
directly to a standard 10.7MHz ceramic filter without additional matching cir-
cuitry.
PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The oscillator signal is fed both to the synthesiser divider chain and to
the downconverting mixer via a buffer amplifier. The BUF pin (Pin 11) has to be
tied to ground. No additional components are necessary. The loop filter is also
realised fully on-chip.
Using high side injection of the local oscillator (L0) for receiving frequencies
below 921MHz and low side injection for frequencies above 921MHz, the
receiving frequency band of 902 to 928MHz can be covered due to the L0 fre-
3 - 10
Specification, December 2006
Functional Description
TDA 5212