TEA5767HN/V3,157 NXP Semiconductors, TEA5767HN/V3,157 Datasheet - Page 13

• Manufacturer Part Number: TEA5767HN/V3,157
• Description: IC STEREO RADIO FM 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of TEA5767HN/V3,157

• Frequency: 76MHz ~ 108MHz
• Modulation Or Protocol: FM
• Current - Receiving: 3.9mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.5 V ~ 5 V
• Operating Temperature: -10°C ~ 60°C
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: TEA5767HN/V3NXP; TEA5767HN/V3NXP

NXP Semiconductors
TEA5767HN_5
Product data sheet
Fig 6. I
BUSENABLE
t
t
t
t
t
t
t
Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.
t
t
t
C
t
t
Remark: The terms SDA and SCL are the corresponding terms used by the I
respectively.
f
r
HD;STA
HIGH
LOW
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
SU;BUSEN
HO;BUSEN
2
= fall time of both SDA and SCL signals: 20 + 0.1C
b
= rise time of both SDA and SCL signals: 20 + 0.1C
C-bus timing diagram
= capacitive load of one bus line: < 400 pF.
= bus free time between a STOP and a START condition: > 600 ns.
= LOW period of the SCL clock > 1300 ns.
= HIGH period of the SCL clock: > 600 ns.
SDA
SCL
= set-up time for a repeated START condition: > 600 ns.
= data set-up time: t
= hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns.
= data hold time: 300 ns < t
= set-up time for STOP condition: > 600 ns.
8.3.1 Data transfer
= bus enable set-up time: t
= bus enable hold time: t
8.3 3-wire bus specification
t
f
t
The 3-wire bus controls the write/read, clock and data lines and operates at a maximum
clock frequency of 400 kHz.
Hint: By using the standby bit the IC can be switched into a low current Standby mode. In
Standby mode the IC must be in the WRITE mode. When the IC is switched to READ
mode, during standby, the IC will hold the data line down. The standby current can be
reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is
deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the
IC maintains normal operation, but is isolated from the clock and data line.
Data sequence: byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this
order).
HD;STA
t
SU;BUSEN
t
LOW
SU;DAT
> 100 ns. If ASIC is used in a standard mode I
HD;DAT
HO;BUSEN
SU;BUSEN
t
r
t
HD;DAT
< 900 ns.
> 10 s.
Rev. 05 — 26 January 2007
> 10 s.
b
b
t
< t
SU;STA
< t
f
Low-power FM stereo radio for handheld applications
f
< 300 ns, where C
< 300 ns, where C
t
HD;STA
b
b
2
= capacitive load on bus line in pF.
C-bus for the DATA and CLOCK signals
= capacitive load on bus line in pF.
t
HIGH
2
C-bus system, t
t
SU;DAT
t
f
t
SU;DAT
SU;STO
TEA5767HN
> 250 ns.
t
BUF
© NXP B.V. 2007. All rights reserved.
t
001aae349
HO;BUSEN
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