SI4322-A0-FTR Silicon Laboratories Inc, SI4322-A0-FTR Datasheet - Page 16

• Manufacturer Part Number: SI4322-A0-FTR
• Description: IC RX FSK UNI 868/915MHZ 16TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4322-A0-FTR

• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -

No
No
Status Read Command
The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of
the control command the Si4322 identifies it as a read command. So as the first bit of the command is received, the receiver starts
to clock out the status bits on the SDO output as follows:
Status Register Read Sequence with FIFO Read Example
No
Not t t t t e e e e e :
No
Definitions of the bits in the above timing diagram:
OFFS(4) -OFFS(0)
nSEL
SCK
SDO
SDI
The FIFO IT bit behaves like a status bit, but generates nIRQ pulse if active. To check whether there is a sufficient amount of data
in the FIFO, the SDO output can be tested. In extreme speed critical applications, it can be useful to read only the first four bits
(FIFO IT - LBD) to clear the FFOV, WK-UP, and LBD bits. During the FIFO access the f
crystal oscillator frequency. If the FIFO is read in this mode the nFFS input must be connected to logic high level.
OFFS(6)
ASAME
WK-UP
DRSSI
FFEM
FFOV
ATGL
FFIT
DQD
CRL
LBD
FIFO IT
0
instruction
FFOV*
interrupt bits
1
The number of data bits in the FIFO has reached the preprogrammed limit
FIFO overflow
Wake-up timer overflow
Low battery detect, the power supply voltage is below the preprogrammed limit
FIFO is empty
The strength of the incoming signal is above the preprogrammed limit
Data Quality Detector detected a good quality signal
Clock recovery lock
Toggling in each AFC cycle
AFC measured twice the same result
MSB of the measured frequency offset (sign of the offset value)
Offset value to be added to the value of the selected center frequency
WK-UP*
2
LBD*
3
FFEM
4
demodulator status bits
DRSSI
5
DQD
6
CRL
7
ATGL
8
ASAME
9
OFFS<6> OFFS<4> OFFS<3> OFFS<2>
(SIGN)
10
AFC status bits
11
SCK
12
cannot be higher than f
13
*NOTE: Marked bits are internally latched.
OFFS<1> OFFS<0>
14
Others are multiplexed out only.
15
FIFO IT
ref
/4, where f
Si4322
ref
is the
16