SI4322-A0-FT Silicon Laboratories Inc, SI4322-A0-FT Datasheet - Page 8

• Manufacturer Part Number: SI4322-A0-FT
• Description: IC RX FSK UNI 868/915MHZ 16TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4322-A0-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 433 MHz to 915 MHz
• Operating Supply Voltage: 2.2 V to 3.8 V
• Mounting Style: SMD/SMT
• Supply Current: 0.5 mA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 4.4mm
• Operating Supply Voltage (typ): 2.5/3.3V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CONTROL INTERFACE
Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin
SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent
is an integer multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data
are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset
(POR) circuit sets default values in all control registers.
The receiver will generate an interrupt request (IRQ) for the microcontroller on the following events:
FFIT and FFOV are applicable only when the FIFO is enabled. To find out why the nIRQ was issued, the status bits should be read out.
Timing Specification
Timing Diagram
Symbol
t
t
t
t
t
t
t
t
CH
CL
SS
SH
SHI
DS
DH
OD
nSEL
SCK
SDI
SDO
• Supply voltage below the preprogrammed value is detected (LBD)
• Wake-up timer timeout (WK-UP)
• FIFO received the preprogrammed amount of bits (FFIT)
• FIFO overflow (FFOV)
t
SS
t
DS
BIT15
BIT15
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
t
DH
t
CH
t
CL
BIT14
BIT14
t
OD
BIT13
BIT13
BIT8
BIT8
BIT7
BIT7
BIT1
BIT1
Minimum value [ns]
BIT0
BIT0
t
SH
25
25
10
10
25
10
5
5
t
SHI
Si4322
8