TRC103 RFM, TRC103 Datasheet - Page 10

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

2.5 Frequency Synthesizer
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver and transmitter sections.
The core of the synthesizer is implemented with an integer-N PLL architecture.
The frequency is set by three divider parameters R, P and S. R is the frequency divider ratio in the reference fre-
quency path. P and S set the frequency divider ratio in the feedback loop of the PLL. The frequency synthesizer
includes a crystal oscillator which provides the frequency reference for the PLL. The equations giving the rela-
tionships between the reference crystal frequency, the local oscillator frequency and RF carrier frequency are
given below:
F
frequency.
F
transmitter. The intermediate frequency used for the second down-conversion of the receiver and the first up-
conversion of the transmitter is equal to 1/8 of F
RF frequency of 869 MHz, F
There are two sets of divider ratio registers: SynthR1[7..0], SynthP1[7..0], SynthS1[7..0], and SynthR2[7..0],
SynthP2[7..0], SynthS2[7..0]. The MCFG00_RF_Frequency[0] bit is used to select which set of registers to use
as the current frequency setting. For frequency hopping applications, this reduces the programming and synthe-
sizer settling time when changing frequencies. While the data is being transmitted, the next frequency is pro-
grammed and ready. When the current transaction is complete, the MCFG00_RF_Frequency[0] bit is comple-
mented and the frequency shifts to the next freq according to the contents of the divider ratio registers. This proc-
ess is repeated for each frequency hop.
2.6 PLL Loop Filter
The loop filter for the frequency synthesizer is shown in Figure 6.
Typical recommended component values for the frequency synthesizer loop filter are provided in Table 4 above.
The loop filter settings are not dependent on the frequency band, so they can be universally used on all designs.
PLL lock status can be provided on Pin 23 by setting the IRQCFG0E_PLL_LOCK_EN[0] bit to a 1 (default).
When the PLL is locked Pin 23 (PLL_LOCK) is high, and when the PLL is unlocked Pin 23 is low. The lock status
of the PLL can also be checked by reading the IRQCFG0E_PLL_LOCK_ST[1] bit. Note that this bit latches high
each time the PLL locks and must be reset by writing a 1 to it.
www.RFM.com
©2009-2010 by RF Monolithics, Inc.
LO
LO
is the first local oscillator (VCO) frequency, F
is the frequency used for the first down-conversion of the receiver and the second up-conversion of the
F
range 64 to 169, and F
F
LO
RF
= F
= 1.125*F
E-mail:
XTAL
*(75*(P + 1) + S)/(R + 1), with P and S in the range 0 to 255, S less than (P + 1), R in the
[e-mail]
PLL Loop Filter
LO
Figure 6
, where F
LO
is 772.4 MHz and the first IF of the receiver is 96.6 MHz.
LO
RF
and F
and F
XTAL
LO
in MHz.
Technical support +1.800.704.6079
are in MHz
LO
XTAL
. As an example, with a crystal frequency of 12.8 MHz and an
is the reference crystal frequency and F
PLL Loop Filter Components
Name
C8
C9
R1
1000 pF
6800 pF
6.8 kΩ
Value
Table 4
Tolerance
±10%
±10%
±5%
RF
is the RF channel
TRC103 - 12/15/10
Page 10 of 64