TRC105 RFM, TRC105 Datasheet
TRC105
Specifications of TRC105
Related parts for TRC105
TRC105 Summary of contents
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... The TRC105 incorporates a set of low-power states to reduce cur- rent consumption and extend battery life. The small size and low power con- sumption of the TRC105 make it ideal for a wide variety of short range radio applications. The TRC105 complies with Directive 2002/95/EC (RoHS). ...
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... Page Configuration Register (PGCFG) .......................................................................................... 40 4.9 Low Battery Configuration Registers (LBCFG)............................................................................... 41 5.0 Electrical Characteristics ....................................................................................................................... 42 5.1 DC Electrical Characteristics .......................................................................................................... 42 5.2 AC Electrical Characteristics .......................................................................................................... 43 6.0 TRC105 Design In Steps....................................................................................................................... 45 6.1 Determining Frequency Specific Hardware Component Values .................................................... 45 6.1.1 SAW Filters and Related Component Values ....................................................................... 45 6.1.2 Voltage Controlled Oscillator Component Values................................................................. 46 www.RFM.com E-mail: info@rfm ...
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... OOK Transmitter Related Configuration Values ................................................................... 52 6.4 Frequency Synthesizer Channel Programming for FSK Modulation.............................................. 53 6.5 Frequency Synthesizer Channel Programming for OOK Modulation............................................. 54 6.6 TRC105 Data Mode Selection and Configuration .......................................................................... 55 6.6.1 Continuous Data Mode ......................................................................................................... 55 6.6.2 Buffered Data Mode .............................................................................................................. 57 6.6.3 Packet Data Mode................................................................................................................. 59 6 ...
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... LOW BATTERY DETECT (LEAVE UNCONNECTED IF NOT USED) CONNECT TO GND MAIN 3.3 V SUPPLY VOLTAGE REGULATED SUPPLY FOR ANALOG CIRCUITRY REGULATED SUPPLY FOR DIGITAL CIRCUITRY REGULATED SUPPLY FOR RF POWER AMP CONNECT TO GND RF I/O RF I/O GROUND PAD ON PKG BOTTOM Table 1 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... Functional Description The TRC105 is a single-chip transceiver that can operate in the 300-510 MHz frequency range. The TRC105 sup- ports two modulation schemes - FSK and OOK. The TRC105’s highly integrated architecture requires a minimum of external components, while maintaining design flexibility. All major RF communication parameters are pro- grammable and most can be dynamically set ...
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... TRC105’s SDI, SDO and SCK pins are shown in Figure 2 (component values shown are for 418.00-434.79 MHz operation; see Tables 57 and 58 for other frequency bands). On-chip regulators provide stable supply voltages to sensitive blocks and allow the TRC105 to be used with supply voltages from 2.1 to 3.6 V. Most blocks are supplied with a voltage below 1.6 V. ...
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... The host microcontroller is provided with a bit rate clock by the TRC105 to clock the data; using this clock to send the data synchronously is mandatory in FSK con- figuration and optional in OOK configuration. In Buffered and Packet data modes the data is first written into the 64-byte FIFO via the SPI interface ...
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... Receiver The TRC105 is set to receive mode when MCFG00_Chip_Mode[7..5] is set to 011. The receiver is based on a double-conversion architecture. The front-end is composed of an LNA and a mixer whose gains are constant. The mixer down-converts the RF signal to an intermediate frequency which is equal to 1/8 of the LO frequency, which in turn is equal to 8/9 of the RF frequency ...
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... Crystal Oscillator Crystal specifications for the TRC105 reference oscillator are given in Table 3. RFM recommends the XTL1020 crystal which is specifically designed for use with the TRC105. Note that crystal frequency error will directly trans- late to carrier frequency, bit rate and frequency deviation error. ...
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... Frequency Synthesizer The TRC105 VCO operating frequency range is covered in six bands. Operation in each band requires a specific VCO inductor value and configuration parameter setting, as shown in Table 4 below: Each of these bands is divided into four subbands to provide a low phase noise VCO frequency trimming mecha- nism ...
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... The lock status of the PLL can also be checked by reading the IRQCFG0E_PLL_ LOCK_ST[1] bit. This bit latches high each time the PLL locks and must be reset by writing it. 3.0 Operating Modes The TRC105 has 5 possible chip-level modes. The chip-level mode is set by MCFG00_Chip_Mode[7..5], which is a 3-bit pattern in the configuration register. Table 7 summarizes the chip-level modes: MCFG00_Chip_Mode[7..5] ...
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... The TRC105 transmitter and receiver sections support three data handling modes of operation: • Continuous mode: each bit transmitted or received is accessed directly at the DATA input/output pin. • Buffered mode: a 64-byte FIFO is used to store each data byte transmitted or received. This data is writ- ten to and read from the FIFO through the SPI bus. ...
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... Dis[6] bit is set to 1 disabling the clock recovery. In this case the demodulator output is directly connected to the DATA pin and the IRQ1 pin (DCLK) is set to low. For proper operation of the TRC105 demodulator in FSK mode, the modulation index meet the following condition: where F is the frequency deviation in hertz (Hz) and BR is the data rate in bits per second (b/s) ...
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... The raw output signal from the demodulator may contain jitter and glitches. Data and clock recovery converts the data output of the demodulator into a glitch-free bit-stream DATA and generates a synchronized clock DCLK to be used for sampling the DATA output as shown in Figure 8. DCLK is available on pin IRQ1 when the TRC105 oper- ates in continuous mode. ...
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... Continuous data mode, but they are used with two additional blocks, the FIFO and SPI. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 9 Figure 10 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... When the TRC105 is in receive mode and MCFG01_Mode [7..6 ] bits are set to 01, all of the blocks described above are enabled normal communication frame the data stream is comprised of a 24-bit preamble, a start pattern and data. Upon receipt of a matching start pattern the receiver recognizes the start of data, strips off the preamble and start pattern, and stores the data in the FIFO for retrieval by the host microcontroller ...
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... TX_STOP to transmit the last bit. If the transmitter is switched off (switched to another mode), the transmission stops immediately even if there is still data in the shift register. In www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. th byte has been written into the FIFO, signal IRQCFG0D_ Figure 12 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... This signal indicates the transmitter FIFO is empty and must be refilled with data to continue transmission. 3.7 IRQ0 and IRQ1 Mapping Two TRC105 outputs are dedicated to host microcontroller interrupts or signaling. The interrupts are IRQ0 and IRQ1 and each have selectable sources. Tables 10, 11, 12 and 13 below summarize the interrupt mapping op- tions ...
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... CLKOUT is enabled, otherwise it is disabled. The output frequency of CLKOUT is defined by the value of the OSCFG1B_Clk_freq[6..2] parameter which gives the frequency divider ratio applied Table 42 for programming details. Note: CLKOUT is disabled when the TRC105 is in sleep mode. If sleep mode is used, the host microcontroller must have provisions to run from its own clock source. ...
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... PKTCFG1C_Pkt_len[6.. value between 65 and 127. The packet format shown in Figure 15 is programma- ble and is made up of the following fields: 1. Preamble 2. Start pattern (network address) 3. Length byte 4. Node address byte (optional) 5. Data bytes 6. Two-byte CRC checksum (optional) www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 13 Figure 14 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... IRQCFG0D_RX_IRQ1[5..4] bits can be set to 00, which maps CRC_OK to IRQ1. After the CRC is checked, the final bytes can be read from the FIFO and the IRQCFG0D_RX_IRQ1[5..4] bits can be reset track www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 15 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... Packet Payload Processing in Transmit and Receive The TRC105 packet handler constructs transmit packets using the payload in the FIFO. In receive, it processes the packets and extracts the payload to the FIFO. Packet processing in transmit and receive are detailed below. ...
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... PKTCFG1D_Node_Addrs[7..0] register and constant 0x00. If the received address byte matches either value, the packet is accepted. An interrupt can also be generated on IRQ0 if the address comparison is successful. The 0x00 address is useful for sending broadcast packets. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... Table 52. In transmit, Manchester encoding is applied only to the payload and CRC parts of the packet. The receiver de- codes the payload and CRC before performing other packet processing tasks. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 16 Figure17 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... The data is scrambled using a random sequence on the transmit side and then descrambled on the receive side using the same sequence. The TRC105 packet handler provides a mechanism for scrambling the packet payload. A 9-bit LFSR is used to generate a random sequence. The payload and the 16-bit CRC checksum are XOR’d with this random sequence as shown in Figure 18 ...
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... If either signal goes high during a byte transmission the counters are reset and the byte must be retransmitted. The configuration interface is selected if nSS_CONFIG is low even if the TRC105 is in buffered mode and nSS_DATA is low (nSS_CONFIG has priority). To configure the transceiver two bytes are required. The first byte contains a 0 start bit, R/W information (1 = read write), 5 bits for the address of the register and a 0 stop bit ...
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... Figure 20 shows the timing diagram for a single byte write sequence to the TRC105 through the SPI configuration interface. Note that nSS_CONFIG must remain low during the transmission of the two bytes (address and data goes high after the first byte, then the next byte will be considered as an address byte. When writing more than one register successively, nSS_CONFIG does not need to have a high-to-low transition between two write se- quences ...
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... E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 23 Figure 24 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... OSCFG1B 0x1A TXCFG1A SYNCFG19 SYNCFG18 SYNCFG17 0x16 SYNCFG16 RXCFG15 RXCFG14 RXCFG13 RXCFG12 RXCFG11 0x10 RXCFG10 IRQCFG0F IRQCFG0E IRQCFG0D 0x0C IRQCFG0C MCFG0B MCFG0A MCFG09 MCFG08 MCFG07 MCFG06 MCFG05 MCFG04 MCFG03 MCFG02 MCFG01 0x00 MCFG00 Table 14 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... IF_Gain 1,0 r/w 10 → below maximum 11 → -13.5 dB below maximum www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. st (lowest) quarter of selected band nd quarter of selected band rd quarter of selected band th (highest) quarter of selected band Table 15 Table 16 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... D ≤ 255. The default value suitable for most applications. F XTAL Bit_Rate_D default = 31 kb/s for F Table 19 Table 20 Description RF frequency 1, R counter R1 = 0x6B (01101011) for 434 MHz Table 21 Technical support +1.800.704.6079 and F are in kHz, DEV XTAL = 12,800 kHz XTAL = 12,800 kHz XTAL = 12,800 kHz XTAL TRC105 - 11/01/10 Page ...
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... Configures the size of the FIFO: 00 → 16 bytes 01 → 32 bytes 10 → 48 bytes 11 → 64 bytes Number of bytes to be written in the FIFO to activate the FIFO_Int_Tx and FIFO_Int_Rx interrupts. Number of bytes = where B is the register value. FIFO_thresh default = 15, Number of bytes = 16 Table 27 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... Buffered or Packet data modes - 0 → IRQ1 mapped to FIFOFULL 1 → IRQ1 is mapped to TX_Stop FIFOFULL 1 r FIFO full (IRQ source) nFIFOEMPY 0 r low when FIFO empty (IRQ source). www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Table 28 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... RSSI threshold level for interrupt. RSSI_thld default is 0x00 www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. 0 → Stop filling FIFO 1 → Start filling FIFO 0 → Transferring bits to the TX modulator 1 → Last bit transferred to the TX modulator Table 29 Table 30 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... L is the integer value of Polyfilt. XTAL = 100 kHz for a 12,800 kHz crystal OPP Table 32 Technical support +1.800.704.6079 is the 3 dB cutoff frequency of the Butterworth filters in CBW is the upper cutoff frequency of polyphase filters in CPP is the center frequency of the OOK polyphase filter in OPP is the XTAL Page TRC105 - 11/01/10 ...
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... Description RSSI 7..0 r RSSI Output www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Table 33 Description OOK fixed threshold or minimum threshold in peak mode. Default is 6 dB. 00000000b → 00000001b → 0.5 dB 00001100b → 11111111b → 127 dB Table 34 Table 35 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... OOK IIR filter coefficients in AVG mode → chip rate / 32*π CAG 01 → chip rate / 8*π CAG 10 → chip rate / 4*π CAG 11 → chip rate / 2*π CAG Table 36 Technical support +1.800.704.6079 is the cutoff frequency for the averaging filter. CAG TRC105 - 11/01/10 Page ...
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... Start pattern most significant byte. This byte is sent first if one or more start pattern bytes are used. Default: 00000000b Table 37 Table 38 Table 39 Table 40 = 200*(F /12800)*((K + 1)/8), where F CTX XTAL is the crystal frequency in kHz, and K is the integer value of TxInterpfilt,. XTAL = 200 kHz CTX Table 41 Technical support +1.800.704.6079 is the 3 dB bandwidth of the transmitter anti-aliasing CTX Page TRC105 - 11/01/10 ...
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... Packet length: the payload size in fixed length mode, the maximum length byte value in variable length mode, and the maximum length byte value in extended variable length packet mode. Pkt_len default: 0000000b Table 43 Description Node address used in filtering received packets in a network. Table 44 Technical support +1.800.704.6079 is the crystal XTAL = F BCO XTAL Page TRC105 - 11/01/10 ...
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... Selects read or write FIFO while in standby mode: 0 → Write FIFO 1 → Read FIFO Not used Register page select (leave set to Page 0 unless configuring low battery detect): 00 → Page 0 01 → Page 1 10 → Not used 11 → Not used Table 46 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... Low battery status: 0 → battery voltage below threshold 1 → battery voltage above threshold Map low battery detect to pin 24: 0 → not mapped 1 → mapped Do not change default bit pattern: 010110 → default bit pattern Table 48 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... V 0.2 0.8 µ µA 0.1 MAX UNITS 3.7 V +125 ° dBm MAX UNITS 3.6 V +85 °C 0 dBm = 3 Test Notes RX_Low_Pwr bit = 1 Vil = 0 V Vih = 3 Iol = -1 mA Ioh = +1 mA Page TRC105 - 11/01/10 ...
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... NRZ NRZ at maximum IF gain at minimum IF gain Test Notes differential output including SAW filter insertion loss programmable => 150 kHz from carrier, no modulation, no modulation no modulation at 600 kHz offset programmable Page TRC105 - 11/01/10 ...
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... Max clock freq 1 ns SPI_CONFIG setup time - ns SPI_DATA setup time - nSS_CONFIG low to SCK rising edge SCK falling edge to nSS_CONFIG high. nSS_DATA low to SCK rising edge SCK falling edge to nSS_DATA high. ns nSS_CONFIG rising to falling edge - ns nSS_DATA rising to falling edge - Page TRC105 - 11/01/10 ...
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... SAW Filters and Related Component Values RFM offers a low-loss SAW RF filter for each of the TRC105’s operating bands listed in Table 57. The part num- bers for these SAW filters and the values of the related tuning components are referenced to Figure 2. The SAW filters are designed to take advantage of the TRC105’ ...
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... The TRC105 RF bit rate is set by the value of the bytes loaded in MCFG03 and MCFG04. For the standard crys- tal frequency of 12.8 MHz: ...
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... The minimum required deviation for good TRC105 FSK performance is DEV Where F is the deviation in kHz and BR is the bit rate in kb/s. Specific to the TRC105, the minimum recom- DEV mended deviation is ±33 kHz, even at low data rates. F the standard crystal frequency of 12.8 MHz: F ...
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... TRC105. The allowed transmitter power level (field strength) depends on the operating frequency and application. See these documents for details. The use of the TRC105 is supported by various radio regulations in almost every geographic location in the world. Please contact RFM’s local Field Application Engineer for additional information. ...
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... Running at a higher bit rate will allow a higher channel hopping rate, which provides more robust operation in a crowded band in tradeoff for less range under quiet band conditions. The TRC105 RF bit rate is set by the value of the bytes loaded in MCFG03 and MCFG04. For the standard crys- tal frequency of 12.8 MHz: ...
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... Technical support +1.800.704.6079 is configured with bits 3..0 in RXCFG10. CPP 65 kHz 82 kHz 109 kHz 137 kHz 157 kHz 184 kHz 211 kHz 234 kHz 262 kHz 321 kHz 378 kHz 414 kHz 458 kHz 514 kHz 676 kHz 987 kHz Page TRC105 - 11/01/10 ...
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... OOK Demodulator Related Configuration Values OOK demodulation in the TRC105 is accomplished by comparing the RSSI to a threshold value. An RSSI value greater than the threshold is “sliced” logic 1, and an RSSI value equal or less than the RSSI value is sliced to a logic 0. The TRC105 provides three threshold options - fixed threshold, average-referenced threshold, and peak-referenced threshold ...
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... TRC105’s data scrambling or Manchester encoding options. The average-referenced threshold run- ning with a chip rate/2*π cutoff frequency is a good choice for the majority of OOK applications. The peak-referenced threshold is generated from the RSSI signal using a fast attack, slow decay peak detector emulation ...
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... MCFG07 P1 MCFG08 S1 MCFG09 R2 MCFG0A P2 MCFG0B S2 Table 68 MCFG00 bits 4..2 Band, MHz 000 300-330 001 330-365 010 365-400 011 400-440 100 440-470 101 470-510 Table 69 Technical support +1.800.704.6079 OOK Rise/Fall Time 2.5/2 µs 5/3 µs 10/6 µs 20/10 µs TRC105 - 11/01/10 Page ...
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... The values and R for OOK receive operation on several common fre- quencies are given in Table 73 for a 0.1 MHz F frequency is provided with the TRC105 development kit. www.RFM.com E-mail: info@rfm.com © ...
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... MCFG01 bits 7..6 select the data mode bit pattern selects Continuous data mode bit pattern selects Buffered data mode. Bit patterns select Packet data mode. The TRC105 configuration details for each data mode are discussed below. ...
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... As shown in Figure 19, two interrupt (control) outputs, IRQ0 and IRQ1, are provided by the TRC105 to coordinate data flow to and from the host microcontroller. In Continuous data mode, one of two signals can be mapped to IRQ0. This mapping is configured in register IRQCFG0D. Bits 7..6 select the signal for IRQ0 in the receive mode. The mapping options for Continuous data mode are summarized in Table 77, where X denotes a don’ ...
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... In Buffered data mode operation, the transmitted and received data bits pass through the SPI port in groups of 8 bits to the internal TRC105 FIFO. Bits flow from the FIFO to the modulator for transmission and are loaded into the FIFO as data is received. As discussed in Sections 3.10 and 3.11, the SPI port can address the data FIFO or the configuration registers ...
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... RF signal ≥ RSSI threshold signal < RSSI Threshold 1 PLL not locked 0 1 PLL_LOCK signal disabled (bit 1 above), Pin 23 set high 0 PLL_LOCK signal enabled Table 79 MCFG0C bits 7..6 FIFO Length Table 80 Technical support +1.800.704.6079 FIFO OK PLL locked 16 bytes 32 bytes 48 bytes 64 bytes Page TRC105 - 11/01/10 ...
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... The host microcontroller can use a countdown on the length byte or detection of the end-of-message byte to determine when all of the message data has been retrieved. 22. As soon as all the message has been retrieved, switch the TRC105 to standby mode by setting MCFG00 bits 7..5 to 001. 23. From standby mode, enter another transmit cycle as outlined in steps 12 through 15, or enter another re- ceive cycle as outlined in steps 16 through 23 ...
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... RF signal ≥ RSSI threshold signal < RSSI Threshold 1 PLL not locked 0 1 PLL_LOCK signal disabled (bit 1 above), Pin 23 set high 0 PLL_LOCK signal enabled Table 82 Technical support +1.800.704.6079 Source Data_Rdy (CRC OK) FIFO_Int_Tx nFIFOEMPY CRC_OK FIFOFULL RSSI_IRQ FIFO_Int_Rx FIFOFULL TX_Stop FIFO OK PLL locked Page TRC105 - 11/01/10 ...
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... PKTCFG1E bits 6..5 Preamble Length 00 1 byte 01 2 bytes 10 3 bytes 11 4 bytes Table 84 Node Address Filtering 00 no filtering 01 only node address accepted 10 node address and 0x00 accepted 11 node address, 0x00 and 0xFF accepted Table 85 Technical support +1.800.704.6079 Page TRC105 - 11/01/10 ...
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... If set to 1, the FIFO data is preserved when the CRC calcula- tion shows an error. PKTCFG1F bit 6 allows the FIFO to be written to or read when the TRC105 is in standby mode. Setting this bit to 0 allows the FIFO to be written and setting this bit to 1 allows read. ...
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... At a data rate of 33.33 kb/ byte packet with a 4 byte preamble and a 4 byte start pattern takes about transmit. Assume that the TRC105 then switches to receive mode for 1 second to listen for a response and returns to sleep. On the basis of reporting every six hours, the ON to sleep duty cycle is about 1:21,259, greatly extending battery life over continuous transmit-receive or even standby operation ...
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... PLL will lock in less than 0.5 ms. PLL lock can be monitored on Pin 23 of the TRC105. The radio can then be switched to either transmit or receive mode. When switching from any other mode back to sleep, the TRC105 will drop to its sleep mode current in less than 1 ms. ...
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... Page TRC105 - 11/01/10 ...
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... Table 83 Technical support +1.800.704.6079 inches minimum nominal maximum 0.199 0.207 0.215 0.199 0.207 0.215 - 13.0 - 0.039 0.043 0.047 0.311 0.315 0.319 - 0.488 - 0.461 0.472 0.484 Page TRC105 - 11/01/10 ...