CYRF7936-40LTXC Cypress Semiconductor Corp, CYRF7936-40LTXC Datasheet - Page 3

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CYRF7936-40LTXC

Manufacturer Part Number
CYRF7936-40LTXC
Description
IC TXRX CYFI 2.4GHZ 40VQFN
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYRF7936-40LTXC

Frequency
2.4GHz
Data Rate - Maximum
1Mbps
Modulation Or Protocol
DSSS, GFSK
Applications
Home/Building Automation, Industrial Control and Monitoring
Power - Output
4dBm
Sensitivity
-97dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
21mA
Current - Transmitting
21mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
Receiving Current
21.2mA
Transmitting Current
26.2mA
Data Rate
1Mbps
Frequency Range
2.4GHz To 2.497GHz
Modulation Type
GFSK
Rf Ic Case Style
QFN
No. Of Pins
40
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Pinouts
Table 1. Pin Description - CYRF7936 40-Pin QFN
Document Number: 001-48013 Rev *E
1
2, 4, 5, 9, 14, 15,
17, 18, 20, 21, 22,
23, 31, 32, 36, 39
3, 7, 16
6, 8, 38
10
11
12
13
19
24
25
26
27
28
29
30
33
34
35
Pin Number
XTAL
NC
V
V
RF
RF
GND
RF
RESV
SS#
SCK
IRQ
MOSI
MISO
XOUT
PACTL
V
RST
V
CC
BAT(0-2)
IO
DD
Name
BIAS
P
N
Type
GND
Pwr
Pwr
Pwr
Pwr
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
RF
XTAL
V
V
BAT1
BAT2
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
V
V
BIAS
NC
NC
NC
NC
Corner
tabs
Default
CC
CC
10
O
O
O
O
Z
1
2
3
4
5
6
7
8
9
I
I
I
I
I
I
I
12-MHz crystal
Connect to GND
V
V
RF I/O 1.8 V reference voltage
Differential RF signal to and from antenna
Ground
Differential RF signal to and from antenna
Must be connected to GND
SPI enable, active LOW assertion. Enables and frames transfers.
SPI clock
Interrupt output (configurable active HIGH or LOW), or GPIO
SPI data input pin master out slave in (MOSI) or serial data (SDAT)
SPI data output pin - master in slave out (MISO), or GPIO (in SPI 3-pin mode).
Tristates when SPI 3PIN = 0 and SS# is deasserted.
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tristates in sleep mode (configure as GPIO drive LOW).
Control signal for external PA, T/R switch, or GPIO
I/O interface voltage, 1.8 V to 3.6 V
Device reset. Internal 10-kΩ pull-down resistor. Active HIGH, typically connect
through a 0.47-μF capacitor to V
is applied to the radio. Otherwise, the radio control register state is unknown.
Decoupling pin for 1.8 V logic regulator, connect through a 0.47-μF capacitor to
GND.
CC
BAT
= 2.4 V to 3.6 V. Typically connected to V
= 1.8 V to 3.6 V. Main supply.
CyFi Transciever
40 lead QFN
* E- PAD Bottom Side
CYRF7936
BAT.
30
29
28
27
26
25
24
23
22
21
Description
Must have RST = 1 event the first time power
SCK
SS
NC
NC
NC
IRQ / GPIO
XOUT / GPIO
MISO / GPIO
MOSI / SDAT
PACTL / GPIO
REG
.
CYRF7936
Page 3 of 22
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