ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 185
![IC AVR MCU 2.4GHZ XCEIVER 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 185 of 555
- Download datasheet (6Mb)
8266B-MCU Wireless-03/11
• Bit 6 – WDIE - Watchdog Timeout Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog
Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog
Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the
Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System
Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the
corresponding interrupt vector will clear WDIE and WDIF automatically by hardware
(the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog
Timer security while using the interrupt. To stay in Interrupt and System Reset Mode,
WDIE must be set after each interrupt. This should however not be done within the
interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out,
a System Reset will be applied.
Table 13-1. Watchdog Timer Configuration
• Bit 4 – WDCE - Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the
WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one,
hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE - Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set (one). To disable an enabled watchdog timer, the following procedure
must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A
logical one must be written to WDE even though it is set to one before the disable
operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This
disables the watchdog. WDE is overridden by WDRF in MCUSR. This means that WDE
is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This
feature ensures multiple resets during conditions causing failure, and a safe start-up
after the failure.
• Bit 5, 2:0 – WDP3:0 – Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer
is running.
Table 13-2. WDP Register Bits
WDTON
1
1
1
1
0
Register Bits
WDP3:0
Note:
(1)
1. WDTON Fuse set to “0“ means programmed and “1” means un-programmed.
WDE
0
0
1
1
x
WDIE
0
1
0
1
x
Value
0x00
0x01
0x02
0x03
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System
Reset Mode
System Reset Mode
Description
Oscillator Cycles 2k, (16ms)
Oscillator Cycles 4k, (32ms)
Oscillator Cycles 8k, (64ms)
Oscillator Cycles 16k, (0.125s)
ATmega128RFA1
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
185
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