AT86RF211SAHW E2V, AT86RF211SAHW Datasheet - Page 33
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AT86RF211SAHW
Manufacturer Part Number
AT86RF211SAHW
Description
IC RF TXRX FSK 400-950MHZ 48TQFP
Manufacturer
E2V
Datasheet
1.AT86RF211SAHW.pdf
(64 pages)
Specifications of AT86RF211SAHW
Frequency
400MHz ~ 950MHz
Data Rate - Maximum
100kbps
Modulation Or Protocol
FSK
Applications
ISM
Power - Output
7dBm ~ 12dBm
Sensitivity
-107dBm
Voltage - Supply
2.4 V ~ 3.6 V
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Current - Transmitting
-
Current - Receiving
-
4.5.3
4.6
4.6.1
4.6.1.1
e2v semiconductors SAS 2008
Control Logic
WL2 programming
Serial Data Interface
Register Interface Format
WL2 can be set as a multiple of WL1 from 0 to 31 WL1.
Table 4-14.
More information is given in the Application Note “Power Management Using the Embedded Stand-
alone Wake-up Mode protocol” reference 2186.
The application microcontroller can control and monitor the AT86RF211S through a synchronous, bidi-
rectional 3-wire serial interface, comprising three signals:
When SLE = 1, the interface is inhibited and the SCK and SDATA (in) values are not propagated into the
IC, reducing power consumption and preventing any risk of parasitic write or read cycle.
A read or write cycle starts when SLE is set to 0 and stops when SLE is set to 1. Only one operation can
be performed during one access cycle, meaning that only one register can be either read or written.
A message comprises three fields:
A variable register length and partial read or write cycles are supported. In the case of partial read or
write cycles, the first data (in or out) is always the register’s MSB.
• SLE signal: enable input
• SCK signal: clock input
• SDATA signal: data in/out
• Address A[3:0]: 4 bits (MSB first)
• R/W: read/write selection
• Data D[31:0]: up to 32 bits (MSB first)
A[3]
WL2[2:0]
(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)
A[2]
ADDRESS
WL2 Programming
2
2
2
2
2
2
2
2
A[1]
A[0]
16 × WL1
31 × WL1
1 × WL1
2 × WL1
3 × WL1
4 × WL1
8 × WL1
Period
R/W
R/W
0
MSB
DATA up to 32 bits (Variable Length)
Simultaneous test of the RSSI and header
D[nbit-1:0]
Comments
0894C–WIRE–11/08
AT86RF211S
LSB
33