T2802-PLH Atmel, T2802-PLH Datasheet - Page 25

• Manufacturer Part Number: T2802-PLH
• Description: IC TRANSCEIVER 2.5GHZ 48-QFN
• Manufacturer: Atmel

Specifications of T2802-PLH

• Frequency: 2.4GHz
• Modulation Or Protocol: WDECT
• Applications: ISM, WDECT(Wideband DECT)
• Power - Output: 3dBm
• Voltage - Supply: 3 V ~ 4.6 V
• Current - Receiving: 85mA
• Current - Transmitting: 58mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Other names: T2802-PLHTR

Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): V
4509F–DECT–10/03
Parameters
RF leakage
Output impedance
Ramp Generator (Pins 36 and 37)
Minimum output voltage
Maximum output voltage
Rise time
Fall time
Lock Detect and Test Mode Output (Pin 5)
Lock detect output, test mode output
Leakage current
Saturation voltage
Auxiliary Regulator (Pins 8, 9 and 10)
Output voltage
Supply voltage rejection
VCO Regulator (Pins 14, 15 and 12)
Output voltage
3-wire Bus
Clock
Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, DATA_HOLD)
(Pins 1, 2, 3, 38, 39, 44, 47 and 48)
High input level
Low input level
High input current
Low input current
Standby Control (Pins 6, 45 and 46)
Power Up
PU_REG = ‘1‘
PU_RX/TX = ‘1‘
PU_PLL = ‘1‘
High input level
Standby
PU_REG = ‘0‘
PU_RX/TX = ‘0‘
PU_PLL = ‘0‘
Low input level
Test Conditions/Pins
In RX mode
At L = 5.6 nH, 2.5 GHz, pin 32
Pin 36 and 37
See bus protocol E6 - E10
C
C
locked = ‘1’,
unlocked = ‘0’
test modes
(see bus protocol E0 ... E2)
V
I
V
V
f
C
V
= ‘1’
= ‘0’
= ‘1’
= ‘0’
Pin 6
Pin 45
Pin 46
Pin 6
Pin 45
Pin 46
OL
Pin10
OH
SREG
Pin10
SVCO
ramp
ramp
Pin8
= 0.5 mA
= 4.6 V
= 0.1 to 10 kHz
= 100 nF
= 270 pF at pin 37
= 270 pF at pin 37
= V
= 3 V, pin 8
= 3 V, pin 15
DC
+ 0.1 V
S_REG
= 3.2 V, T
pp
amb
= 25 ° C
V
V
V
PU_RX/TX,OFF
V
V
PU_REG,OFF
Symbol
V
PU_PLL,OFF
V
REG_VCO
PU_RX/TX
V
PU_REG
Z
SVR
f
P
V
PU_PLL
V
V
Clock
LD
V
V
OUT
REG
I
I
leak
max
I
min
t
t
iH
SL
iL
L
r
iH
f
iL
Min.
1.1
2.9
2.6
1.5
2.0
-5
-5
13 + j40
Typ.
TBD
0.7
3.0
2.7
5
5
6.912
Max.
-47
1.8
0.4
3.1
2.8
0.5
0.7
5
5
5
T2802
dBm
MHz
Unit
µA
dB
µA
µA
µs
µs
W
V
V
V
V
V
V
V
V
V
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