TRC102 RFM, TRC102 Datasheet - Page 12

• Manufacturer Part Number: TRC102
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC102

• Frequency: 400MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 12mA
• Current - Transmitting: 23mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1094-2

The PLL synthesizer is the heart of the operating frequency. It is programmable and completely
integrated, providing all functions required to generate the carriers and tunability for each band. The PLL
requires only a single 10MHz crystal reference source. RF stability is controlled by choosing a crystal
with the particular specifications to satisfy the application. This gives the designer the maximum flexibility
in performance.
The PLL is able to perform manual and automatic calibration to compensate for changes in temperature
or operating voltage. When changing band frequencies, re-calibration must be performed. This can be
done by disabling the synthesizer and re-enabling again through the Power Management Register.
Registers common to the PLL are:
Data Quality Detector (DQD)
The DQD is a unique function of the TRC102. The DQD circuit looks at the prefiltered incoming data and
counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link.
This parameter is programmable through the Data Filter Command Register. The DQD count threshold is
programmable from 0 to 7 counts. The higher the count the lower the quality of the data link. This means
the higher the content of noise spikes in the data stream the more difficult it will be to recover clock
information as well as data.
Valid Data Detector (DDet)
The DDET is an extension of the DQD. When incoming data is detected, it uses the DQD signal, the
Clock Recovery Lock signal, and the Digital RSSI signal to determine if the incoming data is valid. The
DDET looks for valid data transitions at an expected data rate. The desired data rate and the acceptance
criteria for valid data are user programmable through the SPI port. The DDET signal is valid when using
either the internal receive FIFO or an external pin to capture baseband data. The DDET has three modes
of operation: slow, medium, fast. Each mode is dependent on what signals it uses to determine valid data
as well as the number of incoming preamble bits present at the beginning of the packet. The DDET can
be disabled by the user so that only raw data from the comparator comes out, or it can be set to accept
only a preset range of data rates and data quality. The DDET saves battery power and time for a host
microprocessor because it will not wake up the microprocessor unless there is valid data present. See
the Receiver Control Register for a detailed description of the setup for valid data.
Receive Signal Strength Indicator (RSSI)
The TRC102 provides an analog RSSI and a digital RSSI. The digital RSSI threshold is programmable
through the Receiver Control Register and is readable through the Status Register only. When an
incoming signal is stronger than the preprogrammed threshold, the digital RSSI bit in the Status Register
is set.
www.RFM.com
©by RF Monolithics, Inc.
•
•
•
•
•
Power Management Register
Configuration Register
Frequency Setting Register
Automatic Frequency Adjust Register
Transmit Configuration Register
Email: [e-mail]
TRC102 - 4/8/08
Page 12 of 51