TRC102 RFM, TRC102 Datasheet - Page 17

• Manufacturer Part Number: TRC102
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC102

• Frequency: 400MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 12mA
• Current - Transmitting: 23mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1094-2

FIFTXRX
Bit
15
Status Register (Read Only)
The Status Register provides feedback for:
Note: The Status Register read command begins with a logic ‘0’ where all other register commands begin with a logic ‘1’.
Bit [15]:FIFTXRX – When set, indicates the transmit register is ready to receive the next byte for transmission (Transmit Mode) or
Bit [14]:POR – When set, Power-on Reset occurred. (Cleared after Status Reg read).
Bit [13]:FIFOV/UR – When set, indicates transmit register under run or register overwrite (Transmit Mode) or receive FIFO overflow
Bit [12]:WKINT – When set, indicates a Wake-up timer overflow. (Cleared after Status Reg read).
Bit [11]:EXINT – When set, indicates a High to Low logic level change on interrupt pin (pin 16). (Cleared after Status Reg read).
Bit [10]:LB – When set, indicates the supply voltage is below the preprogrammed limit. See Battery Detect Threshold and Clock
Bit [9]:FIFEMP – When set, indicates receive FIFO is empty.
Bit [8]:RSSI(Rx) – When set and chip in receive mode, this bit indicates that the incoming RF signal is above the preprogrammed
Bit [7]:GDQD – When set, indicates good data quality.
Bit [6]:CRLCK – When set, indicates Clock Recovery is locked.
Bit [5]:AFATGL – For each AFC cycle run, this bit will toggle between logic ‘1’ and logic ‘0’.
Bit [4]:OFFSGN – Indicates the difference in frequency is higher (logic ‘1’) or lower (logic ‘0’) than the chip frequency.
Bit [3..0]:OFF[3..0] – The offset value to be added to the frequency control word (internal PLL).
AFA has to be disabled during the read by clearing the "AFEN" bit in the AFA Register (bit 0).
To read the status register, initiate a command beginning with a ‘0’ and read the remaining bits on the SDO line. All other
commands begin with a ‘1’ so the TRC102 recognizes a command vs. status. See figure 4 for timing reference.
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POR
Bit
14
AT(TX) – When in transmit mode this bit indicates that the antenna tuning circuit has detected a strong enough RF signal.
FIFOV/UR
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Bit
13
Output Register.
FIFO ready/full/empty/under run/overwrite
POR
Interrupt state
Low Battery
Good Data Quality
Digital RSSI signal level
Clock Recovery
Frequency Offset value and sign
AFA
Digital RSSI limit.
that the Rx FIFO has reached the preprogrammed limit (Receive Mode). This bit is multiplexed and dependent
on whether you are in the respective Transmit or Receive mode. (Cleared when FIFO read).
WKINT
(Receive Mode). (Cleared after Status Reg read).
Bit
12
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INTRST
Bit
11
Bit
10
LB
FIFEMP
Bit
9
RSSI/AT
Bit
8
GDQD
Bit
7
CRLCK
Bit
6
AFATGL
Bit
5
In order to get accurate values the
OFFSGN
Bit
4
OFF3
Bit
3
TRC102 - 4/8/08
Page 17 of 51
OFF2
Bit
2
OFF1
Bit
1
OFF0
Bit
0