MC13192FC Freescale Semiconductor, MC13192FC Datasheet - Page 5

• Manufacturer Part Number: MC13192FC
• Description: IC RF TRANSCEIVER 2.4GHZ 32-QFN
• Manufacturer: Freescale Semiconductor

Specifications of MC13192FC

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: AMR, HID, HVAC, ISM
• Power - Output: -3dBm ~ 4dBm
• Sensitivity: -92dBm
• Voltage - Supply: 2 V ~ 3.4 V
• Current - Receiving: 37mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (typ): 2.5/3.3V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: Q1982232

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The MC13192 has two data transfer modes:
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1
Figure 3
MC13192 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame
Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and
appended to the end of the data.
4.2
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
If the MC13192 is in packet mode, the data is processed as an entire packet. The MCU is notified that an
entire packet has been received via an interrupt.
If the MC13192 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis.
Figure 4
about -57 dBm input power which is well above 802.15.4 Standard requirements.
Freescale Semiconductor
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
Data Transfer Modes
shows CCA reported power level versus input power. Note that CCA reported power saturates at
shows the packet structure of the MC13192. Payloads of up to 125 bytes are supported. The
Packet Structure
Receive Path Description
4 bytes
Preamble
1 byte
SFD
Figure 3. MC13192 Packet Structure
1 byte
MC13192 Technical Data, Rev. 3.3
FLI
125 bytes maximum
Payload Data
2 bytes
FCS
Data Transfer Modes
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