SI4010-B1-GS Silicon Laboratories Inc, SI4010-B1-GS Datasheet - Page 48
SI4010-B1-GS
Manufacturer Part Number
SI4010-B1-GS
Description
IC TX 27-960MHZ FSK 3.6V 14SOIC
Manufacturer
Silicon Laboratories Inc
Series
EZRadio®r
Type
ISM Transmitterr
Datasheets
1.4010-DAAKF_434.pdf
(2 pages)
2.SI4010-B1-GS.pdf
(160 pages)
3.SI4010-C2-GS.pdf
(156 pages)
Specifications of SI4010-B1-GS
Package / Case
14-SOIC (0.154", 3.90mm Width)
Frequency
27MHz ~ 960MHz
Applications
Garage Openers, RKE, Security Alarms
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
100 kBaud
Power - Output
10dBm
Current - Transmitting
19.8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
4kB RAM
Features
8051 MCU Core, Crystal-less Operation
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
27 MHz to 960 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V to 3.6 V
Supply Current
10 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1974-5
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Si4010
SFR Definition 12.2. ODS_TIMING
SFR Address = 0xAA
48
Name
Reset
7:5
4:3
2:0
Bit
Type
Bit
WIDTH[2:0]
ODS_CK_
GROUP_
DIV[2:0]
EDGE_
Name
ODS_
ODS_
TIME
[1:0]
R/W
ODS_GROUP_WIDTH[2:0]
7
0
Controls Symbol Group width, from 2–8 Symbols.
Set to 4 to transmit 5 symbol groups obtained from 4/5 encoding. Or set to 7 to send
8 symbol group obtained from Manchester encoding of 4 bits. Note that
ods_group_width can be changed dynamically prior to writing the ODS_DATA regis-
ter, should you want to (for example) add 2 more symbols to the end of a
transmission which was previously using 8 symbol groups.
Controls PA Edge Time.
Additional division factor in range 1-4 (ods_edge time+1). PA controlled edge rates
are: 8*(ods_ck_div+1)*(ods_edge_time+1)/25 MHz. When clk_ods is in range of 3-
8 MHz, edge rate can be selected from 1us to 10.7us. Study has indicated that in the
worst case (20Kbps Manchester), edge rates somewhat higher than 4us are needed.
Controls the Clock of the ODS.
Sets the division factor of the 24 MHz system clock to produce clk for the ODS mod-
ule.
Division factors are 1–8 (ods_ck_div+1). Generally should select factor which
produces serializer clock in range of ~ 3-8 MHz
R/W
6
0
R/W
5
0
ODS_EDGE_TIME
R/W
Rev. 0.5
4
0
[1:0]
Function
R/W
3
0
R/W
2
0
ODS_CK_DIV[2:0]
R/W
1
0
R/W
0
0
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