SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet

IC TX 27-960MHZ FSK 3.6V 10MSOP

SI4010-C2-GT

Manufacturer Part Number
SI4010-C2-GT
Description
IC TX 27-960MHZ FSK 3.6V 10MSOP
Manufacturer
Silicon Laboratories Inc
Series
EZRadio®r
Type
Crystalless SoC RF Transmitterr
Datasheet

Specifications of SI4010-C2-GT

Package / Case
10-MSOP
Mfg Application Notes
SI4010 Calculator Spreadsheet AppNote
Frequency
27MHz ~ 960MHz
Applications
Garage Openers, RKE, Security Alarms
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
100 kBaud
Power - Output
10dBm
Current - Transmitting
19.8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
4kB RAM
Features
8051 MCU Core, Crystal-less Operation
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
27 MHz to 960 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V to 3.6 V
Supply Current
14.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1997-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4010-C2-GT,,95,MSOP8,SILICON LABS,,,2020+
0
Part Number:
SI4010-C2-GTR
Manufacturer:
ST
Quantity:
1 000
C
Features
Applications
Description
The Si4010 is a fully integrated crystal-less CMOS SoC RF transmitter with an
embedded CIP-51 8051 MCU. The device can operate over the –40 to 85 °C
temperature range without requiring an external crystal reference source reducing
board area and BOM cost. The device includes an 8 kB non volatile memory block
for programming the user's application along with a 12 kB ROM of embedded
support code for use in the user's application. The Si4010 includes Silicon
Laboratories' 2-wire C2 Debug and Programming interface, which allows
customers to download their code during the development stage into the on-board
RAM for testing and debug prior to programming the NVM.
The Si4010 is designed for low power battery applications with standby currents of
less than 10 nA to optimize battery life and features automatic wake on button
press support to efficiently move from the standby to active mode state with
minimal customer code support. Built in AES-128 hardware encryption along with
a 128-bit EEPROM can be used to create robust data encryption of the
transmitted packets. A unique 4-byte serial number is programmed into each
device ensuring non-overlapping device identifiers.
The RF transmitter features a high efficiency PA capable of delivering output
power up to +10 dBm and includes an automatic antenna tuning algorithm. This
algorithm adjusts the antenna tuning at the start of each packet transmission for
optimal output power minimizing the impact of antenna impedance changes due
to the remote being held in a user hand. The devices supports FSK and OOK
modulations and includes automatic output power shaping to reduce spectral
spreading and ease regulatory compliance. The output frequency can be adjusted
via software over the entire 27 to 960 MHz range. The output data rate is software
adjustable up to a maximum rate of 100 kbps.
Rev. 1.0 2/11
Crystal-less operation

High-Speed 8051 µC Core








Extensive Digital Peripherals








Garage and gate door openers
Remote keyless entry
R YS TA L
Optional crystal oscillator input
Pipeline instruction architecture
70% of instructions in 1 or 2 clocks
Up to 24 MIPs with 24 MHz clock
4 kB RAM/8kB NVM
128 bit EEPROM
256 byte of internal data RAM
12 kB ROM embedded functions
8 byte low leakage RAM
128 bit AES accelerator
5/9 GPIO with wakeup functionality
LED driver
Data serializer
High-speed frequency counter
On-chip debugging: C2
Unique 4 byte serial number
Ultra low-power sleep timer
-
L E S S
S
O
Copyright © 2011 by Silicon Laboratories
C RF T
Home automation and security
Wireless remote controls
Single Coin-Cell Battery Operation


High-performance RF transmitter






Analog Peripherals


Temperature range –40 to +85 °C
Automotive quality option, 
AEC-Q100 (Pending final
qualification testing)
10-pin MSOP/14-pin SOIC
Supply voltage: 1.8 to 3.6 V
Standby current < 10 nA
Frequency range: 27–960 MHz
+10 dBm output power,
adjustable
Automatic antenna tuning
Symbol rate up to 100 kbps
FSK/OOK modulation
Manchester, NRZ, 4/5 encoder
LDO regulator with POR circuit
Battery voltage monitor
R A N S M I T T E R
Patents pending
GPIO0/XTAL
VPP/GPIO0/XTAL
S i 4 0 1 0 - C 2
Ordering Information:
GND
TXM
VDD
TXP
GPIO9 1
GPIO7
GND
TXM
VDD
TXP
Pin Assignments
1
2
3
4
5
10-Pin MSOP
14-Pin SOIC
See page 15.
2
3
4
5
6
7
Si4010-GS
Si4010-GT
14 GPIO8
13 GPIO1
12 GPIO2
11
10
9
8
GPIO3
C2DAT/GPIO4
C2CLK/LED
GPIO6
10 GPIO1
9 GPIO2
8
7
6
Si4010
GPIO3
GPIO4
LED

SI4010-C2-GT Summary of contents

Page 1

... Remote keyless entry  Description The Si4010 is a fully integrated crystal-less CMOS SoC RF transmitter with an embedded CIP-51 8051 MCU. The device can operate over the – °C temperature range without requiring an external crystal reference source reducing board area and BOM cost. The device includes non volatile memory block for programming the user's application along with ROM of embedded support code for use in the user's application ...

Page 2

... Si4010-C2 Functional Block Diagram VDD CR2032 COIN CELL GND 1.8 – 3.6 V VDD LED GPIO INTERFACE PUSH BUTTONS 4/8 2 LDO REGULATOR DIVIDER PA FSK OOK INTEGRATED 8051 MCU I/O RAM/ NVM ROM 8 Kbyte Rev. 1.0 Si4010 TXP LOOP ANTENNA TXM EEPROM 128-bit ...

Page 3

... PCB Land Pattern 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9. PCB Land Pattern 14-pin SOIC Package 10. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 11. System Description 11.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.2. Setting Basic Si4010 Transmit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.3. Applications Programming Interface (API) Commands . . . . . . . . . . . . . . . . . . . . . . 35 12. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.1. Register Description .38 13. Output Data Serializer (ODS ...

Page 4

... Si4010-C2 22.1. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 22.1.1. Instruction and CPU Timing................................................................................ 56 22.2. CIP-51 Register Descriptions .61 23. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 23.1. Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.2. Internal Data Memory 23.3. External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.4. General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.5. Bit Addressable Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 23.6. Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 23.7. Special Function Registers (SFR .67 23 ...

Page 5

... IDE Development Environment and Debugging Chain . . . . . . . . . . . . . . . . . . . . . . . . 151 36.1. Functionality Limitations While Using IDE Development Environment . . . . . . . . . 151 36.2. Chip Shutdown Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 36.3. LED Driver Usage while Using IDE Debugging Chain . . . . . . . . . . . . . . . . . . . . . . 152 37. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Rev. 1.0 Si4010-C2 5 ...

Page 6

... Figure 1.1. Si4010 Block Diagram ............................................................................................ 12 Figure 2.1. Test Block Diagram with 10-Pin MSOP ................................................................. 13 Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator .................................. 14 Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator ..... 14 Figure 1. Si4010 Top Marking .................................................................................................. 16 Figure 2. Si4010 Top Marking .................................................................................................. 17 Figure 7 ...

Page 7

... Table 9.1. PCB Land Pattern Dimensions ................................................................................ 27 Table 10.1. Recommended Operating Conditions ................................................................... 28 Table 10.2. Absolute Maximum Ratings Table 10.3. DC Characteristics ................................................................................................29 Table 10.4. Si4010 RF Transmitter Characteristics ................................................................. 30 Table 10.5. Low Battery Detector Characteristics .................................................................... 31 Table 10.6. Optional Crystal Oscillator Characteristics ............................................................ 31 Table 10.7. EEPROM Characteristics ...................................................................................... 32 Table 10.8. Low Power Oscillator Characteristics .................................................................... 32 Table 10 ...

Page 8

... Si4010-C2 L XREG XREG Definition 12.2. wPA_CAP .......................................................................................... 38 XREG Definition 12.3. bPA_TRIM .......................................................................................... 39 XREG Definition 15.1. bLPOSC_TRIM .................................................................................. 47 XREG Definition 16.1. bXO_CTRL ......................................................................................... 49 XREG Definition 17.3. IFC_COUNT ....................................................................................... 53 XREG Definition 23.1. abMTP_RDATA[16] ........................................................................... 68 8 EGISTERS Rev. 1.0 ...

Page 9

... Si4010-C2 L SFR EGISTERS SFR Definition 12.1. PA_LVL ...................................................................................................38 SFR Definition 13.1. ODS_CTRL ............................................................................................. 41 SFR Definition 13.2. ODS_TIMING ..........................................................................................42 SFR Definition 13.3. ODS_DATA ............................................................................................. 43 SFR Definition 13.4. ODS_RATEL ........................................................................................... 43 SFR Definition 13.5. ODS_RATEH ..........................................................................................44 SFR Definition 13.6. ODS_WARM1 ......................................................................................... 44 SFR Definition 13.7. ODS_WARM2 ......................................................................................... 45 SFR Definition 14.1. LC_FSK ...................................................................................................46 SFR Definition 15.2. SYSGEN .................................................................................................48 SFR Definition 17 ...

Page 10

... Si4010-C2 SFR Definition 33.1. RTC_CTRL ........................................................................................... 130 SFR Definition 34.1. TMR_CLKSEL ....................................................................................... 139 SFR Definition 34.2. TMR2CTRL ........................................................................................... 140 SFR Definition 34.3. TMR2RL ................................................................................................ 142 SFR Definition 34.4. TMR2RH ...............................................................................................142 SFR Definition 34.5. TMR2L .................................................................................................. 143 SFR Definition 34.6. TMR2H .................................................................................................. 143 SFR Definition 34.7. TMR3CTRL ........................................................................................... 144 SFR Definition 34 ...

Page 11

... Like all wireless devices, users are responsible for complying with applicable local regulatory requirements for radio transmissions. The embedded CIP-51 8051 MCU provides the core functionality of the Si4010. User software has com- plete control of all peripherals, and may individually shut down any or all peripherals for power savings. A space on-chip one-time programmable NVM memory is available to store the user program and can also store unique transmit IDs ...

Page 12

... AES 128b ACCEL GPIO0/XTAL/VPP C2 GPIO1 GPIO2 GPIO3 GPIO4/C2DAT PORT CONTR GPIO5/C2CLK/LED GPIO6 14P SOIC GPIO7 Package GPIO8 Only GPIO9 Figure 1.1. Si4010 Block Diagram 12 MEMORY RF ANALOG CORE CONTROLLER NVM EEPROM HVRAM 8 KB 128-bit 8 Byte OOK ODS DIVIDER FSK LCOSC LPOSC SFR ...

Page 13

... Test Circuit TEST MATCHING EQUIPMENT NETWORK Figure 2.1. Test Block Diagram with 10-Pin MSOP 1 10 GPIO0 GPIO1 2 9 GND GPIO2 TXM GPIO3 Si4010- TXP GPIO4 5 6 VDD LED Rev. 1.0 Si4010-C2 GP1 GP2 TESTER GP3 INTERFACE GP4 GP5 13 ...

Page 14

... Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator 3.2. Si4010 with an External Crystal in a 4-Button RKE System with LED Indicator CR2032 COIN CELL C3 1 LOOP ANTENNA Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator 14 1 GPI0 GPIO1 2 GND GPIO2 U1 ...

Page 15

... Ordering Information Table 4.1. Product Selection Guide Si4010-C2- Si4010-C2- Si4010-C2- Si4010-C2- Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. 2. Assumes LED driver is used and no external crystal. 3. AEC Q100 qualification is pending. 256 8 128 256 8 128 ...

Page 16

... Line 1 Customer Part Number YY = Year WW = Work Week Line 2 TTTTTT = Trace Code 16 Figure 1. Si4010 Top Marking Description "e3" Pb-Free Symbol Si4010C2 Assigned by the Assembly House. Corresponds to the year and work week of the assembly date. Manufacturing code characters from the Markings section of the Assembly Purchase Order form ...

Page 17

... Characters Line 1 Device Part Number Line 2 TTTT = Trace Code Line 3 YWW = Date Code Figure 2. Si4010 Top Marking Description 10C2 Line 2 from the "Markings" section of the Assembly Purchase Order form. Date Code assigned by the assembly house Last Digit of Current Year (Ex: 2008 = Work Week of Mold Date. ...

Page 18

... GPIO0/XTAL 2 GND 3, 4 TXM, TXP 5 VDD 6 LED GPIO[4: GPIO1 2 9 GPIO2 Si4010- GPIO3 4 7 GPIO4 5 6 LED Description General purpose input pin. Can be configured as an input pin for a crystal. Ground. Connect to ground plane on PCB. Transmitter differential outputs. Power. Dedicated LED driver. ...

Page 19

... GND Ground. Connect to ground plane on PCB. 3 TXM Transmitter differential output. 4 TXP Transmitter differential output. 5 VDD Power. 6 C2CLK C2 clock interface. 7 C2DAT C2 data input/output pin GPIO[3:1] General purpose input/output pins GPIO1 2 9 GPIO2 Si4010- GPIO3 4 7 C2DAT/GPIO4 5 6 C2CLK/LED Description Rev. 1.0 Si4010-C2 19 ...

Page 20

... TXM, TXP 6 VDD 7,8 GPIO[7:6] 9 LED 10,11,12,13 GPIO[4:1] 14 GPIO8 20 14 GPIO8 2 13 GPIO1 3 12 GPIO2 Si4010- GPIO3 5 10 GPIO4 6 9 LED 7 8 GPIO6 Description General purpose input/output pin General purpose input pin. Can be configured as an input pin for a crystal Ground. Connect to ground plane on PCB ...

Page 21

... Description General purpose input/output pin +6.5 V required for NVM (OTP) Memory programming Ground. Connect to ground plane on PCB Transmitter differential outputs Power General purpose input/output pins C2 clock interface C2 data input/output pin General purpose input/output pins General purpose input/output pin Rev. 1.0 Si4010-C2 21 ...

Page 22

... Si4010-C2 7. Package Specifications 7.1. 10-Pin MSOP Figure 7.1 illustrates the package details for the Si4010, 10-pin MSOP package. Table 7.1 lists the values for the dimensions shown in the illustration. Figure 7.1. 10-Pin MSOP Package Table 7.1. Package Dimensions Symbol Millimeters Min ...

Page 23

... SOIC Package Figure 7.2 illustrates the package details for the Si4010, 14-pin SOIC package. Table 7.2 lists the values for the dimensions shown in the illustration. Figure 7.2. 14-Pin SOIC Package Table 7.2. Package Dimensions Symbol Min A — A1 0. ...

Page 24

... Si4010-C2 8. PCB Land Pattern 10-Pin MSOP Figure 8.1. 10-Pin MSOP Recommended PCB Land Pattern 24 Rev. 1.0 ...

Page 25

... The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD- 020 specification for Small Body Components. Rev. 1.0 Si4010-C2 MAX 4.40 REF 0.50 BSC — 0.30 1 ...

Page 26

... Si4010-C2 9. PCB Land Pattern 14-pin SOIC Package   Figure 9.1. 14-Pin SOIC Recommended PCB Land Pattern 26 Rev. 1.0 ...

Page 27

... The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD- 020 specification for Small Body Components. Rev. 1.0 Si4010-C2 MAX 5.40 1.27 BSC 0.60 1.55 27 ...

Page 28

... Si4010-C2 10. Electrical Characteristics Table 10.1. Recommended Operating Conditions Parameter Symbol Supply Voltage V Supply Voltage Slew Rate Ambient Temperature Digital Input Range *Note: Recommend bypass capacitor = 1 µF; slew rate measured 1 V < V Table 10.2. Absolute Maximum Ratings Parameter Supply Voltage 3 Input Current ...

Page 29

... All GPIO floating or held high V > 200 mV OUT Trip point at 0. Trip point at 0. 500 µA SOURCE I = 500 µA SINK Rev. 1.0 Si4010-C2 Min Typ Max Unit — 14.2 — mA — 11.3 — mA — 19.8 — mA — 14.1 — mA — 700 — ...

Page 30

... Optimum differential load is equal to 3.5 V/(11.5 mA/2 x 4/PI) = 480 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 480 4. Total NVM copy time = (NVM copy Boot Time per kB) x (NVM data in kB). ...

Page 31

... Optimum differential load is equal to 3.5 V/(11.5 mA/2 x 4/PI) = 480 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 480 4. Total NVM copy time = (NVM copy Boot Time per kB) x (NVM data in kB). ...

Page 32

... Si4010-C2 Table 10.7. EEPROM Characteristics Parameter Program Time Independent of number of bits Count per 32-Bit Counter Write Endurance (per bit)* Note: *API uses coding technique to achieve write endurance of 1M cycles per bit. Table 10.8. Low Power Oscillator Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings. ...

Page 33

... V. The Si4010 is awakened from standby mode by a falling edge to ground on any one of the GPIO pins. In addition, the Si4010 has a low-power sleep timer for applications where the device is required to wake up and periodically check for events instead of being wakened by a GPIO falling edge ...

Page 34

... Si4010-C2 The Si4010 has three timing sources. The LCOSC is the most accurate timing source native to the chip. Each device is factory trimmed and programmed at Silicon Labs to produce a frequency accuracy of better than ±150 ppm over the temperature range °C and ±250 ppm over the industrial range of –40 to +85 ° ...

Page 35

... Silicon Labs website (www.silabs.com) in the Support/Document Library/EZRadio section, and it is part of each Si4010 development kit. Consult “AN547: Si4010 Calculator Spreadsheet Usage” for details of the calculator operations. ...

Page 36

... Si401X transmitters. With proper filtering and layout techniques, the Si4010 can conform to US FCC part 15.231 and European EN 300 220 regulations. Edge rate control is also included for OOK mode to reduce harmonics that may otherwise violate government regulations ...

Page 37

... In this alpha equation, the 4 is derived from 1 dBm/0.25 dBm per step in bLevel. Thus, the units of alpha are (LSB steps in bLevel)/(change in temp). Beta can be determined using the Si4010 calculator spreadsheet. These two parameters should be entered as parameters to the API to provide accurate adjustments to the radiated power ...

Page 38

... Si4010-C2 12.1. Register Description SFR Definition 12.1. PA_LVL Bit 7 6 PA_LVL_NSLICE[4:0] Name Type Reset SFR Address = 0xCE Bit Name PA_LVL_ Number of Slices Enabled in the PA Driver. This parameter determines the output current drive of the PA. Programming this 7:3 NSLICE register directly is not recommended. Use the vPa_Setup() API function instead. ...

Page 39

... This parameter boost the bias current of the PA by 1.5 times up to 10.5 mA. The 4 DRV values entered into this register come from the Power Amplifier Module API. This bit should be set without changing the other bits. 3:0 Reserved Reserved PA_MAX_ Reserved Reserved DRV R/W 0 Function Rev. 1.0 Si4010- Reserved Reserved 39 ...

Page 40

... Si4010-C2 13. Output Data Serializer (ODS) 13.1. Description The ODS block is responsible for synchronizing the output data to the required data rate and maintaining a steady data flow during transmission. The serializer accomplishes the following functions: Controls the edge rate of the PA on/off transitions.  ...

Page 41

... Force PA On. .0: Normal operation. 1 FORCE_PA 1: Force PA on. In addition, PA_LVL_NSLICE[4:0] in PA_LVL register is passed directly through the serializer, unchanged. Enable the Serializer. 0 ODS_EN 0: Disable the ODS. 1: Enable the ODS FSK_ FORCE_ FORCE_ MODE LC R/W R/W R Function Rev. 1.0 Si4010- FORCE_ ODS_EN DIV PA R/W R/W R ...

Page 42

... Sets the division factor of the 24 MHz system clock to produce clk for the ODS mod- ule. ODS_CK_ 2:0 Division factors are 1–8 (ods_ck_div+1). Generally should select factor which DIV[2:0] produces serializer clock in range of ~ 3-8 MHz. Using the Si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended ODS_EDGE_TIME ...

Page 43

... R/W R/W Type 0 0 Reset SFR Address = 0xAC Bit Name ODS_RATEL Lower Byte of the 15-bit Wide ODS Data Rate Field. 7:0 [7:0] Symbol rate produced by the serializer is 24MHz/(ods_datarate*(ods_ck_div+1 ODS_DATA[7:0] R Function ODS_RATEL[7:0] R/W R/W R Function Rev. 1.0 Si4010- R/W R/W R ...

Page 44

... OOK Zero bit to OOK One bit. Set this value in a way that the 3:0 WARM_ warm-up interval of the PA should be 1us for a given ODS clock rate. Interval is PA[3:0] directly in clk_ods cycles. Interval = ods_warm_pa x (ods_ck_div+1)/24 MHz Using the Si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended ...

Page 45

... LCOSC should be 125 µs for a given ODS clock 3:0 WARM_ rate. LC[3:0] Interval clk_ods cycles resolution Interval = 64 x ods_warm_lc x (ods_ck_div+1)/24 MHz Using the Si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended ODS_WARM_LC[3:0] 0 ...

Page 46

... VCO is based on the Silicon Laboratories Si500 crystal-less oscillator chip and forms the core of the Si4010s' crystal-less operation. After this device is factory trimmed, the VCO fre- quency is the most accurate frequency on the chip and sets the chips transmit frequency stability unless an external crystal oscillator is used. The device achieves ± ...

Page 47

... XREG Definition 15.1. bLPOSC_TRIM Bit 7 6 Name Type 1 1 Reset XREG Address = 0x4002 Bit Name Low Power (24 MHz) Oscillator Trimming. LPOSC_ 7:0 ±16% range with 0.14 % resolution. Setting all the bits to low will maximize the fre- TRIM[7:0] quency of operation LPOSC_TRIM[7:0] R Function Rev. 1.0 Si4010- ...

Page 48

... Si4010-C2 SFR Definition 15.2. SYSGEN Bit 7 6 Name SYSGEN_ Re-served PWR_1ST SHUT- DOWN R/W R Type 0 0 Reset SFR Address = 0xBE Bit Name System General Shutdown. Setting this bit causes shutdown of MCU and most analog. Recovery from this is via  SYSGEN_ falling edge on any GPIO, which results in a power up and a power on reset. This is ...

Page 49

... If Cload > 14 pF, XO_LOWCAP bit of the bXO_CTRL register have to be set this case, the input  capacitance of the XTAL pin of the Si4010 is approximately 5.5 pF (Cload – 5.5)pF capacitor should be placed externally across the crystal terminals. If Cload < XO_LOWCAP bit of the bXO_CTRL register have to be set this case, the input  ...

Page 50

... Si4010-C2 17. Frequency Counter The frequency counter allows the measurement of the ratio of two selected clock sources: a low frequency clock which defines a counting interval, and a high frequency clock which is counted. The frequency counter consists of an interval counter, driven by one of the six clock sources. Programming of the interval counter determines how long the main counter will count one of the two high speed clocks, LC oscillator or DIVIDER output ...

Page 51

... The main function of the Frequency counter is to aid the frequency casting operation, however it can be used for measuring purposes, using the calibrated LC oscillator as a time base. One example is enhancing the accuracy of the internal timers of the MCU. See “AN526: Si4010 API Additional Library Description” for more details. ...

Page 52

... Si4010-C2 17.1. Register Description SFR Definition 17.1. FC_CTRL Bit 7 6 Name FC_DONE FC_BUSY FC_DIV_ R/W R/W Type 0 0 Reset SFR Address = 0x9B Bit Name Frequency Counter Done. Counting done, interrupt generation level signal. Must be cleared by software ISR also cleared written to fc_busy, which denotes the start of the next count. Any ...

Page 53

... Counter output value. Accessed as 4 bytes (long word) in big endian fashion. 3:0 IFC_COUNT[0:3] Upper bits [31:23] are read as 0. When the counter is running and the value is read then the current on the fly value will be read FC_INTERVAL[5:0] R/W 0 Function 2 1 IFC_COUNT[3:0] R 0x00 0x00 Function Rev. 1.0 Si4010- 0x00 53 ...

Page 54

... Si4010-C2 18. Sleep Timer The Si4010 includes a very low-power sleep timer that can be used to support the transmit duty cycle requirements of the ETSI specification or self-wakeup for button independent applications. It consist of a low speed (~2.1 kHz), very low power oscillator with a 24 bit down counter. When programmed to its maxi- mum interval it takes ~2 ...

Page 55

... Program and Data Memory Security l DATA BUS B REGISTER STACK POINTER TMP1 TMP2 SRAM ADDRESS SRAM ALU REGISTER DATA BUS SFR_ADDRESS BUFFER D8 SFR_CONTROL SFR BUS D8 SFR_WRITE_DATA D8 INTERFACE SFR_READ_DATA MEM_ADDRESS D8 MEM_CONTROL MEMORY MEM_WRITE_DATA A16 INTERFACE MEM_READ_DATA PIPELINE D8 INTERRUPT INTERFACE EMULATION_IRQ D8 D8 REGISTER Rev. 1.0 Si4010-C2 SYSTEM_IRQs 55 ...

Page 56

... Si4010-C2 With the CIP-51's maximum system clock at 24 MHz, it has a peak throughput of 24 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions in the function of the required clock cycles. Clocks to Execute 1 Number of Instructions 26 22.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ ...

Page 57

... direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte Si4010-C2 Bytes Rev. 1.0 Clock Cycles ...

Page 58

... Si4010-C2 Table 22.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry SWAP A Swap nibbles of A Data Transfer ...

Page 59

... Compare immediate to Register and jump if not equal CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Si4010-C2 Bytes Rev. 1.0 Clock Cycles ...

Page 60

... Si4010-C2 Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct—8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– ...

Page 61

... The DPL register is the low byte of the 16-bit DPTR. SFR Definition 22.2. DPH Bit 7 6 Name Type 0 0 Reset SFR Address = 0x83 Bit Name Data Pointer High. 7:0 DPH[7:0] The DPH register is the high byte of the 16-bit DPTR DPL[7:0] R Function DPH[7:0] R Function Rev. 1.0 Si4010- ...

Page 62

... Si4010-C2 SFR Definition 22.3. SP Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name Stack Pointer. 7:0 SP[7:0] The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset. ...

Page 63

... SFR Definition 22.5. B Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF0; Bit-Addressable Bit Name B Register. 7:0 B[7:0] This register serves as a second accumulator for certain arithmetic operations B[7:0] R Function Rev. 1.0 Si4010- ...

Page 64

... Si4010-C2 SFR Definition 22.6. PSW Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name Carry Flag This bit is set when the last arithmetic operation resulted in a carry (addition bor- row (subtraction cleared to logic 0 by all other arithmetic operations. ...

Page 65

... Memory Organization The memory organization of the Si4010 is similar to that of a standard 8051. There are two separate mem- ory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. However, this device is unique since it has the pro- gram and data memory spaces combined into one ...

Page 66

... Si4010-C2 23.1. Program Memory Program memory consists of 4.5 kB for RAM and ROM. The device employs a unified CODE/XDATA RAM memory. On 8051 architecture the external data memory (XDATA) space is physically different from the program memory (CODE); they can be accessed with different instructions. On this device the RAM can store both CODE and XDATA at any location ...

Page 67

... NVM memory is only accessible indirectly through Silicon Labs provided API functions for NVM access ini- tialization and read of formatted blocks of data generated by the NVM programmer. Programming of the NVM can be only done by Silicon Labs provided tools not possible to program the NVM by writing to registers. See “System Boot and NVM Programming” on page 69 for details. Si4010-C2 Rev. 1.0 67 ...

Page 68

... Si4010-C2 The maximum number of read operations of the NVM memory is limited, but this limitation has effect only in extreme conditions. Consult the electrical specification section in this document, and with “ANxxx NVM Reliability Analysis.” 23.10. MTP (EEPROM) Memory The MTP memory is a special block not organized as a usual memory. The memory output is mapped to the XDATA address space as a XREG register (abMTP_RDATA[16]) 16 byte read only array at addresses 0x4040 ...

Page 69

... For debugging purposes user will not program the NVM, but will use the RAM for code development. In that case the device will only contain factory settings and go through much shorter startup routine, which would take less than finish. Si4010-C2 Rev. 1.0 69 ...

Page 70

... Si4010-C2 24.2. Reset Reset circuitry allows the controller to be easily placed in a predefined default condition. See “Reset Sources” on page 106 for details. 24.3. Chip Program Levels The boot process starts by reading the NVM configuration bytes in the Factory region of NVM. The infor- mation about the programmed level of the chip is read first and the boot process acts accordingly. After boot, the program level of the chip can be read as NVM_BLOWN[2:0] field in the PROT0_CTRL  ...

Page 71

... The User App region is the data region available to the user for a load to be loaded at runtime by the user program. The user will have to call the API NVM copy routine in that case. “AN518: Si4010 Memory Over- lay Technique" describes this process in detail. In such a scenario, this NVM region will not be loaded by boot, but by the user application. That region of NVM is labeled as User App region in Figure 24.1, “ ...

Page 72

... Si4010-C2 NVM 8KB 0xE000 Set by the factory setup wBoot_NvmUserBeg Optional gap User App (App Use) 0xFFC0 0xFFFF Figure 24.1. NVM Address Map 24.5. Device Boot Process The boot process works in the following sequence: 1. Boot is invoked by cycling power to the internals of the chip (which includes power cycle to the whole chip), waking up by button press, by the sleep timer pressing a Reset button in the IDE development platform ...

Page 73

... RAM size available for user application and about the final status of the boot process. The visual representation of the RAM is in Figure 24.2. The detailed explanation of the boot control data variables are in Table 24.1 to SFR Definition 24.1. Si4010-C2 Rev. 1.0 73 ...

Page 74

... Si4010-C2 The user code or user development environment need to pay attention to the content of the following vari- ables. All are stored in big endian fashion (MSB at the lower address): wBoot_DpramTrimBeg .. this variable points to the first occupied (by factory data) address of RAM.  Therefore, the user development platform needs to read this variable to determine what the available RAM area for user CODE/XDATA is ...

Page 75

... CODE/XDATA RAM 4.5KB 0x0000 User CODE/ XDATA Factory XDATA 0x11F3 wBoot_DpramTrimBeg 0x11F5 wBoot_NvmUserBeg 0x11F7 Boot_AfterTrimExe Boot_PatchExe 0x11FD wBoot_NvmCopyAddr 0x11FF bBoot_BootStat Figure 24.2. CODE/XDATA RAM Address Map Rev. 1.0 Si4010-C2 75 ...

Page 76

... Si4010-C2 24.8. Boot Status Variables End of the CODE/XDATA RAM are reserved for boot status variables. The user must pay attention to the content of the wBoot_DpramTrimBeg variable. Its content points to the first reserved address for Factory Silicon Labs use. Important: The CODE/XDATA area from this address on (increasing address) is reserved and must not be overwritten by User NVM load at boot time nor by user application at runtime ...

Page 77

... BOOT_FLAGS register through IDE (see View -> Debug Windows -> SFR -> Boot window). Don’t forget to press the Refresh IDE button for the change to take effect. Then until the power to the part is cycled the part would behave as a Factory part BS_ERR_FACTORY[2: Function Rev. 1.0 Si4010- BS_ERR_ BS_ERR_ USER_ USER_ NEXT FIRST ...

Page 78

... Si4010-C2 SFR Definition 24.2. BOOT_FLAGS Bit 7 6 Reserved Reserved BOOT_ Name TRIM_ R/W R/W Type 0 0 Reset SFR Address = 0xDD Bit Name 7:6 Reserved Reserved. Force User Part to Act as a Factory Part. For User part only: During the boot process load only Factory values and stop. By other ...

Page 79

... NVM gets programmed with a proper data structures such that the data values pro- vided in the IntelHEX files will appear at the RAM and IRAM addresses specified in the IntelHEX input file after the boot is done. 0x0000 RAM 4.5K 0x11FF 0x4000 0x7000 IRAM 256B 0x8000 0xFFFF Rev. 1.0 Si4010-C2 79 ...

Page 80

... Si4010-C2 Note that by using the unified CODE/XDATA memory and by mapping the IRAM to the boot process address space the user can initialize both XDATA and IRAM variables directly from the User NVM load without the need for running any startup code to do variable initializations, resulting in the saving of a code size ...

Page 81

... IRAM gets also cleared completely outside of the register bank 0 (bottom 8 registers). This ensures that there is no lingering User code or data values, like keys, in any of the RAM’s. This bit is in PROT3_CTRL.MEM_C2_PROT and it corresponds to RAM Clear checkbox on the NVM programmer GUI. Si4010-C2 Description Rev. 1.0 81 ...

Page 82

... Si4010-C2 Table 24.2. Run Chip Retest Protection Flags: NVM Programmer Flag Name mtp_c2_prot Protect MTP. When set then both Wr and Rd access to MTP is disabled. Forces boot process to set MTP_PROT=1 to disable MTP communication completely. Reading from MTP returns 0x00 values, writing is not possible. Customer may want to set this option if there is a sensitive information written into the MTP EEPROM during the lifetime of the part ...

Page 83

... User the user code is loaded from NVM to RAM, but is not 1 USER_CONT executed automatically. If this bit is set, then the user load is executed automatically after boot. This bit corresponds to Exe User Boot checkbox on the NVM programmer GUI. 0 Reserved Reserved BOOT_XO Reserved _ENA 0x0 Function Rev. 1.0 Si4010- USER_ Reserved CONT ...

Page 84

... Si4010-C2 24.13. Chip Protection Control Register The boot process sets the value of the device protection and configuration SFR register, PROT0_CTRL. The user can read the register and check the programming level of the device as well as protections set to control access to the NVM and MTP memories and C2 interface. The register is user writable, but once a value written to any of the bits in the register it cannot be written as 0 ...

Page 85

... The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as imple- menting additional SFRs used to configure and access the sub-systems unique to the Si4010-C2. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. ...

Page 86

... Si4010-C2 Table 25.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 Accumulator ACC 0xF0 B Register B 0xDD Boot Flags BOOT_FLAGS 0x8F Clock Output Settings CLKOUT_SET 0x83 Data Pointer High DPH 0x82 Data Pointer Low ...

Page 87

... TMR3CTRL 0x95 Timer/Counter 3 High TMR3H 0x94 Timer/Counter 3Low TMR3L 0x93 Timer/Counter 3 Reload High TMR3RH 0x92 Timer/Counter 3 Reload Low TMR3RL 0xC9 Timer Source Clock Selection TMR_CLKSEL Si4010-C2 Description Rev. 1.0 Page 100 122 84 64 127 130 105 62 48 105 140 143 143 ...

Page 88

... Si4010-C2 25.2. XREG Registers The chip contains another set of registers implemented in the XREG memory area. These registers are located in the XDATA address space, addressable by MOVX instructions only. From CPU perspective regular external memory. The advantage of the XREG registers is that they are viewed by the CPU as a regular memory. Therefore, they can be declared as different data types, structures, array of bytes, and so on ...

Page 89

... BYTE ... 0x404f Note: Multiple byte variables, if they are not arrays, are stored in big endian ..  MSB byte stored on lower address. Arrays are stored with byte index [0] at lower address. Rev. 1.0 Si4010-C2 Name Byte Order bLPOSC_TRIM <reserved> IFC_COUNT MSB Byte LSB Byte ...

Page 90

... Si4010-C2 XREGs are listed in alphabetical order. Register Address 0x4008 lFC_COUNT 0x4002 bLPOSC_TRIM 0X4040 abMTP_RDATA[16] 0x400C wPA_CAP 0x4012 bPA_TRIM 0x4016 bXO_CTRL Description of the XREG register fields on the previous pages includes only the used register bits. The fields are aligned towards the LSB byte of the XREG register. If the actual XREG register is wider then the field described the missing bits towards MSB byte are all read as 0's and writing to them has no effect ...

Page 91

... Interrupts The Si4010 device includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt- pending flag is set to logic ‘1’. ...

Page 92

... Si4010-C2 26.1. MCU Interrupt Sources and Vectors The device supports 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend- ing flag to logic ‘1’. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ- ated vector addresses, priority order, and control bits are summarized in Table 26 ...

Page 93

... TMR3INTH (TMR3CTRL.7) 6 INT1_FLAG (INT_FLAGS.1) 7 N/A 8 N/A 9 FC_DONE (FC_CTRL.7) 10 VOID0_FLAG (INT_FLAGS.3) 11 VOID1_FLAG (INT_FLAGS.4) Rev. 1.0 Si4010-C2 Enable Flag Priority Control N/A Always Always Enabled Highest N EINT0 (IE.0) PINT0 (IP.0) Y ETMR2 PTMR2 (IE.1) (IP.1) N EDMD (IE.2) PDMD (IP.2) N ERTC (IE.3) PRTC (IP.3) N EODS (IE ...

Page 94

... Si4010-C2 SFR Definition 26.1. IE Bit EINT1 ETMR3 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ...

Page 95

... Timer 2 interrupt set to high priority level. External Edge Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0 PINT0 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level PODS PRTC R/W R/W R Function Rev. 1.0 Si4010- PDMD PTMR2 PINT0 R/W R/W R ...

Page 96

... Si4010-C2 SFR Definition 26.3. EIE1 Bit 7 6 Name Reserved Reserved Reserved R R Type 0 0 Reset SFR Address = 0xE6 Bit Name 7:5 Reserved Read as 0x0. Write has no effect. Enable VOID1 Interrupt (Reserved). This bit sets the VOID1 interrupt.(Reserved) 4 EVOID1 0: Disable VOID1 interrupts. ...

Page 97

... This bit sets the priority of the Frequency Counter interrupt. 2 PFC 0: Frequency Counter interrupt set to low priority level. 1: Frequency Counter interrupt set to high priority level. 1:0 Reserved Reset value 0x0 must not be changed PVOID1 PVOID0 PFC R/W R/W R Function Rev. 1.0 Si4010- Reserved R ...

Page 98

... Si4010-C2 SFR Definition 26.5. INT_FLAGS Bit 7 6 Name Reserved Reserved Reserved R R Type 0 0 Reset SFR Address = 0xBF Bit Name 7:5 Reserved Read as 0x0. Write has no effect. VOID1_ Spare Interrupt Flag (can be used freely by the user application software). 4 FLAG Interrupt can be invoked by software only by writing 1 here. ...

Page 99

... MHz/128 the user to recognize possible external interrupt delays associated with sampling of the INT0 and INT1 by the system clock at the current, user selected, clock frequency. The INT1 and INT0 internal signals are also used as capture event signals for timer 3 and 2, respectively, if they are running in capture mode. Si4010-C2 Rev. 1.0 99 ...

Page 100

... Si4010-C2 SFR Definition 26.6. PORT_INTCFG Bit 7 6 NEG_ SEL_INT1[2:0] Name INT1 R/W Type 0 0 Reset SFR Address = 0xB7 Bit Name Negative INT1 Polarity. This bit selects whether the selected INT1 GPIO input will get inverted or pass as is NEG_ before going to the edge detector. Note the edge detector detects either the rising 7 edge or both ...

Page 101

... Each analog peripheral must be shut down individually prior to entering Stop mode. Stop mode can only be terminated by an external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution based on the program level of the chip. The system clock is not stopped when in Stop mode. Si4010-C2 Rev. 1.0 101 ...

Page 102

... Si4010-C2 SFR Definition 27.1. PCON Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name General Purpose Flags 5–0. 7:2 GF[5:0] These are general purpose flags for use under software control. Stop Mode Select. 1 STOP Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. ...

Page 103

... If the Silicon Labs device API AES implementation is used by the user application, all the AES accelerator communication is handled by the API functions and is hidden from the user. ; Invoke a GF multiply ; At least single cycle wait instruction ; Read the result ; Invoke a SBox conversion ; At least single cycle wait instruction ; Read the result Rev. 1.0 Si4010-C2 103 ...

Page 104

... Si4010-C2 SFR Definition 28.1. GFM_DATA Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0x84 Bit Name GFM Multiplier Data Processing. Writing of a value here registers the data for processing. Processed data is regis- GFM_DATA 7:0 tered into the same register with single CLK_SYS cycle delay. Read from this reg- [7:0] ister reads the processed multiplied data ...

Page 105

... Reserved. Read as 0x0. Write has no effect. 4 Reserved Reserved. Do not write to this bit. AES SBox Hardware Logic Control. AES_DECRYPT 0: SBox is set for encryption. 1: SBox is set for decryption. Reserved Reserved. Do not change these values SBOX_DATA[7:0] R/W R/W R Function R/W R Function Rev. 1.0 Si4010- R/W R/W R R/W R/W R 105 ...

Page 106

... Si4010-C2 29. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. There is only one external reset source for the device, which is power on reset. It gets invoked at two occasions: 1. Power is supplied to the device. This means connecting the power supply to disconnected device or cycling the external power to the device ...

Page 107

... Software Reset There is no traditional software reset on the Si4010, but a similar result can be achieved by setting up the sleep timer and then putting the device into shutdown mode. This action effective disconnects power to the internal systems of the device. Once the sleep time expires it will wake the Si4010, which will have the same effect as a power on reset to the device creating a software reset ...

Page 108

... Si4010-C2 30. Port Input/Output Digital resources are available through I/O pins. The number of I/O depends on the package: 10 pin package .. 6 port pins organized as 6 bottom bits of Port 0.  14 pin package .. 10 port pins organized as a full 8-bit Port 0 and 2 bottom bits of Port 1.  ...

Page 109

... GPIO[2:1]. Table 30.1. 10–Pin Mode Package Pin Package Pin Number Name 1 GPIO0/XO 10 GPIO1 9 GPIO2 8 GPIO3 7 GPIO4 6 GPIO5/LED Table 30.2. 14–Pin Mode Package Pin Package Pin Number Name 2 GPIO0/XO 13 GPIO1 12 GPIO2 11 GPIO3 10 GPIO4 9 GPIO5/LED 8 GPIO6 7 GPIO7 14 GPIO8 1 GPIO9 Rev. 1.0 Si4010-C2 109 ...

Page 110

... Si4010-C2 Digital logic Wr: PORT_MATRIX Wr: PORT_ROFF PORT_STROBE Rd: PORT_MATRIX Rd: PORT_ROFF gpio_in[n] gpio_push_pull[n] port_push_pull[n] port_oe[n] gpio_dataout[n] port_dataout[n] Figure 30.2. GPIO[3:1] Functional Diagram Functional diagram of the other GPIO ports is in Figure 30. the general GPIO circuit that can be forced by digital control to have limited functionality (e.g., as input only, etc.). ...

Page 111

... LED has to be isolated from the pin as shown in Figure 35.1 and Figure 35.2. The LED is disabled during debugging. C2 FOB 1 button button button 2 button C2DAT button 3 C2CLK LED 4 button button button button Rev. 1.0 Si4010-C2 Can Drive Pullup Roff Low During Option Sleep 111 ...

Page 112

... Si4010-C2 30.2. Pullup Roff Option There is an option to disable the weak pullup pad resistors. This feature is called Roff option. The Roff option is controlled directly by the GPIO pads and persist when the chip is in the shutdown mode. Control of the Roff control bit in the GPIO is described in section 30.4. Pullup Roff and Matrix Mode Option Con- trol ...

Page 113

... Wr: PORT_MATRIX PORT_STROBE E Figure 30.4. Push Button Organization in Matrix Mode Si4010-C2 GPIO[9] GPIO[8] GPIO[7] GPIO[6] GPIO[0] GPIO[4] GPIO[3] GPIO[2] GPIO[1] Rev. 1.0 14 pin package only Pushbuttons connecting the crossing wires: = 113 ...

Page 114

... Si4010-C2 30.4. Pullup Roff and Matrix Mode Option Control Both Roff and Matrix mode options are controlled by the GPIO pad itself. The control is implemented as 2 bit latch inside of the GPIO pads. Both options stay in their used defined states during chip shutdown. In other words, if the chip is in shutdown mode, the digital logic does not have power, but the two GPIO latches keep the user set values of those options ...

Page 115

... The lower the priority number, the higher the functional priority. For example, if the functional- ity with priority 1 is programmed, then controls selecting functionality of priority 2 and above will be ignored no matter what the control settings are. Si4010-C2 ; Turn GPIO[3:1] as inputs ; Set Matrix mode and keep resistors ...

Page 116

... Si4010-C2 Table 30.4. GPIO Special Roles Control and Order GPIO Roles Order 0 VPP XO_CTRL.XO_ENA GPIO 3 P0.0 fixed as input only 1 GPIO 1 P0.1 P0CON.1 Matrix, Roff Ind* PORT_CTRL 2 GPIO 1 P0.2 P0CON.2 Matrix, Roff Ind* PORT_CTRL 3 Reference 1 PORT_SET.PORT_REFEN clk_ref GPIO 2 P0.3 P0CON.3 Matrix Ind* PORT_CTRL ...

Page 117

... The user then can hit the Connect button on the IDE to connect to the chip again. For the IDE to be able to connect to the chip the LED must not be driven (not lit). VDD 50k PORT_CTRL Figure 30.5. GPIO[5] LED Driver Block Diagram VDD GPIO[5]/LED Debug LED disable 2 P0 Rev. 1.0 Si4010-C2 117 ...

Page 118

... Si4010-C2 SFR Definition 30.1. P0 Bit 7 6 Name R/W R/W Type 1 1 Reset SFR Address = 0x80 Bit Name Port 0 Register, GPIO[7:0], Bit Addressable. Write appears at the GPIO[7:0] outputs, read reads directly the GPIO input values. Write output low value 1 .. output open-drain or high drive value in push-pull mode Read: 0 ...

Page 119

... Write appears at the GPIO[15:8] outputs, read reads directly the GPIO input values. 7:0 P1[7:0] Same as for P0. Only GPIO[9:8] are used, write to the rest of the register has no effect, read returns 0 at those bits P0CON[7:0] R/W R/W R Function P1[7:0] R/W R/W R Function Rev. 1.0 Si4010- R/W R/W R R/W R/W R 119 ...

Page 120

... Si4010-C2 SFR Definition 30.4. P1CON Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xA5 Bit Name Port 1 Register GPIO[15:8], Bit Addressable. This bit controls configuration of each corresponding output bit in P1 open-drain, pull up resistor connected (see PORT_ROFF) 7:0 P1CON[7: push-pull, pull up resistor disabled If the pin to be input, it must be configured as open-drain and 1 has to be written as output value to it ...

Page 121

... The actual turning of the LED on and off is controlled by the GPIO[5] output bit in P0. PORT_LED 1:0 [1:0] 00: LED off 01: LED current = 0.62*600uA 10: LED current = 1.00*600uA 11: LED current = 1.62*600uA PORT_ PORT_5_ PORT_ DRV2X MID- RANGE RANGE R/W R/W R/W — Function Rev. 1.0 Si4010- PORT_LED[1:0] MID- R/W R/W R 121 ...

Page 122

... Si4010-C2 SFR Definition 30.7. PORT_SET Bit 7 6 EDGE_ EDGE_ PORT_CLKOUT[1:0] Name INT1 INT0 R/W R/W Type 0 0 Reset SFR Address = 0xB6 Bit Name Edge Control for INT1. EDGE_ This bit controls whether single edge or both edges invoke the interrupt. 7 INT1 0: Single edge, polarity specified by NEG_INT1 in PORT_INTCFG. ...

Page 123

... CLKOUT_DIV recommended to fix all the settings before enabling the output clock generator. The master enable is PORT_CLKEN bit in the PORT_SET register. CLKOUT_SET Enable Clear Divide by 24MHz CLKOUT_DIV[4:0] Figure 31.1. Output Clock Generator Block Diagram Si4010-C2 Symmetry 1:1 Duty Cycle PORT_SET Rev. 1.0 GPIO[6] GPIO[4] 123 ...

Page 124

... Si4010-C2 31.1. Register Description SFR Definition 31.1. CLKOUT_SET Bit 7 6 Name CLKOUT_ CLKOUT_ CLKOUT_ CLR INV R/W R/W Type 0 0 Reset SFR Address = 0x8F Bit Name CLKOUT Clear. Write 1 to this bit clears the generated clock divider. The generated clock output is forced to 0 ...

Page 125

... To monitor when the output gets idle monitor the CLKOUT_CLR bit of this register. The CLKOUT_DIV bit can be changed any time. The new setting will take effect only after the current period finishes. For the new setting to take effect immediately see CLKOUT_CLR. Si4010-C2 Function Rev. 1.0 125 ...

Page 126

... Si4010-C2 32. Control and System Setting Registers The following are general system setting control registers as well as general purpose scratch pad regis- ters. GPR_CTRL and GPR_DATA can be used as a general purpose 2 byte SFR register. They do not con- trol any hardware on the device. SFR Definition 32.1. GPR_CTRL ...

Page 127

... Tx shift register. ODS No Data. 2 ODS_NODATA Supplementary flag that the output digital serializer (ODS) Tx shift register ran out of data and there is nothing else to transmit. 1:0 Reserved Reserved. Can read either XO_ ODS_ ODS_NOD CKGOOD EMPTY ATA Function Rev. 1.0 Si4010- Reserved Reserved 127 ...

Page 128

... Si4010-C2 33. Real Time Clock Timer The Si4010 device contains a real time clock (RTC) timer. This dedicated timer provides accurate interrupt request pulses in precise time intervals. The device does not contain any hardware nor any battery backed up real time clock. The purpose of RTC timer is to provide accurate time intervals for user application at run time, not an absolute real calendar time ...

Page 129

... TMR2 and TMR3, so there is a need to have separate control over the rtc_tick generator clearing. To get the RTC tick generator running the RTC_ENA=1 must be set. Therefore, even if the RTC interrupt is not used, the RTC timer must be enabled if the user wants to use the rtc_tick as a clock source for TMR2 or TMR3. Si4010-C2 Rev. 1.0 129 ...

Page 130

... Si4010-C2 SFR Definition 33.1. RTC_CTRL Bit 7 6 Name RTC_INT RTC_ENA RTC_CLR Reserved R/W R/W Type 0 0 Reset SFR Address = 0x9C Bit Name Real Time Clock Interrupt Flag. 7 RTC_INT Set after the time interval set by RTC_DIV field elapses. Software must clear the flag. ...

Page 131

... Timers 2 and 3 The Si4010 device includes two identical timers, Timer 2 (TMR2) and Timer 3 (TMR3). Since the timers are identical, the description will refer to Timer 2 (TMR2). The reader can replace the TMR2 with TMR3 in the text to get the description of Timer 3 (TMR3). The description refers to a “Timer” alias for either TMR2 or TMR3 ...

Page 132

... Si4010-C2 34.1. Interrupt Flag Generation Timer 2 has a single interrupt signal going to interrupt controller. Internally, there are 2 interrupt flags, TMR2INTH for high half of the timer and TMR2INTL for low half of the timer, which are combined to gener- ate the final interrupt signal. The low half has a local interrupt flag enable TMR2INTL_EN control bit. ...

Page 133

... Also note that if the capture timer is stopped (TMR2L_RUN=0) the capture event still captures the current counter registers (TMR2H:TMR2L) into the timer reload registers (TMR2H:TMR2RL) and sets the flag TMR2INTH. TMR2L overflow TMR2L TMR2H TMR2RL TMR2RH Reload Rev. 1.0 Si4010-C2 Interrupt TMR2INTH TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2L_CAP TMR2H_RUN TMR2L_RUN ...

Page 134

... Si4010-C2 TMR_CLKSEL 2 TMR2L_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us) 3 Capture INT0 INT1 for TMR3 Figure 34.3. Capture 16-bit Mode Block Diagram (Wide Mode) 34.4. 8-Bit Timer/Timer Mode (Split Mode) When TMR2SPLIT=1, the timer operates as two independent 8-bit timers. Each of the 8-bit timers can independently operate in either 8-bit timer or 8-bit capture modes ...

Page 135

... If the capture timer is stopped (TMR2L_RUN=0), the capture event still captures the cur- rent counter register TMR2L into the reload register TMR2RL and sets the flag TRM2INTL. Same indepen- dently applies to the upper half TMR2H with its respective registers and flags. Si4010-C2 TMR2INTH TMR2H ...

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... Si4010-C2 TMR_CLKSEL 2 TMR2H_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us TMR2L_RUN INT0 INT1 for TMR3 Figure 34.5. Two 8-bit Timers in Capture/Capture Configuration (Split Mode) 34.6. 8-Bit Timer/Capture Mode (Split Mode) When TMR2SPLIT=1, TMR2L_CAP=1 and TMR2H_CAP=0, the split timers operate one in 8-bit timer mode and the other in 8-bit capture mode ...

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... TMR_CLKSEL 2 TMR2H_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us TMR2L_RUN INT0 INT1 for TMR3 Figure 34.6. Two 8-Bit TImers in Timer/Capture Configuration (Split Mode) TMR2H TMR2INTH TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2RH TMR2L_CAP Reload TMR2H_RUN TMR2L_RUN TMR2L Capture TMR2RL Rev. 1.0 Si4010-C2 Interrupt 137 ...

Page 138

... Si4010-C2 TMR_CLKSEL 2 TMR2H_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us TMR2L_RUN INT0 INT1 for TMR3 Figure 34.7. Two 8-Bit Timers In Capture/Timer Configuration (Split Mode) 138 TMR2INTH TMR2H TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP Capture TMR2RH TMR2L_CAP TMR2H_RUN TMR2L_RUN TMR2L TMR2RL Reload Rev. 1.0 Interrupt ...

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... RTC_TICK = 5.33 µs 11: RTC_PULSE = 100 µs Timer 2 Low Byte Mode Select. Timer 2 low half in split mode or full timer in wide mode clock selection. TMR2L_ 00: CLK_SYS 1:0 MODE 01: CLK_SYS/12 10: RTC_TICK = 5.33 µs 11: RTC_PULSE = 100 µ TMR3L_MODE TMR2H_MODE R/W R Function Rev. 1.0 Si4010- TMR2L_MODE R 139 ...

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... Si4010-C2 SFR Definition 34.2. TMR2CTRL Bit 7 6 TMR2 TMR2 Name INTH INTL INTL_EN R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name Timer 2 High Byte Interrupt Flag. TMR2 Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide ...

Page 141

... Timer 2 High Byte Run Model. TMR2H_ 1 TMR2H high byte enable in split configuration. Ignored if timer operates in wide con- RUN figuration. Timer 2 Low Byte Run Model. TMR2L_ 0 TMR2L low byte enable in split configuration, whole timer enable in wide configura- RUN tion. Si4010-C2 Function Rev. 1.0 141 ...

Page 142

... Si4010-C2 SFR Definition 34.3. TMR2RL Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name Timer 2 Capture/Reload Register Low Byte. TMR2RL holds the low byte of the capture/reload value for Timer 2. LSB Byte. Two halves are not double buffered. Write to each of the halves takes effect immedi- ...

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... SFR Address = 0xCD Bit Name Timer 2 High Byte Actual Timer Value. 7:0 TMR2H[7:0] In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer bit mode, TMR2H contains the 8-bit high byte timer value TMR2L[7:0] R Function TMR2H[7:0] R Function Rev. 1.0 Si4010- 143 ...

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... Si4010-C2 SFR Definition 34.7. TMR3CTRL Bit 7 6 TMR3 TMR3 Name INTH INTL INTL_EN R/W R/W Type 0 0 Reset SFR Address = 0xB9 ; Bit Name Timer 3 High Byte Interrupt Flag. TMR3 Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide ...

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... Timer 3 High Byte Run Model. TMR3H_ 1 TMR3H high byte enable in split configuration, whole timer enable in wide configura- RUN tion. Timer 3 Low Byte Run Model. TMR3L_ 0 TMR3L low byte enable in split configuration, whole timer enable in wide configura- RUN tion. Si4010-C2 Function Rev. 1.0 145 ...

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... Si4010-C2 SFR Definition 34.8. TMR3RL Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBA Bit Name Timer 3 Capture/Reload Register Low Byte. TMR3RL holds the low byte of the capture/reload value for Timer 3. LSB Byte. Two halves are not double buffered. Write to each of the halves takes effect immedi- ...

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... SFR Address = 0xBD Bit Name Timer 3 High Byte Actual Timer Value. 7:0 TMR3H[7:0] In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer bit mode, TMR3H contains the 8-bit high byte timer value TMR3L[7:0] R Function TMR3H[7:0] R Function Rev. 1.0 Si4010- 147 ...

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... Si4010-C2 35. C2 Interface The devices include an on-chip Silicon Laboratories 2-Wire (C2) debug interface in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CLK) and a bi- directional C2 data signal (C2DAT) to transfer information between the device and a host system. The C2 interface is intended to be used by the Silicon Labs or third party development tools ...

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... Instead of the USB debug adapter the user can also use Silicon Labs ToolStick development tool. The ToolStick has a PCB edge 14 pin connector. Connection in between the device and the ToolStick for soft- ware development and debugging is in Figure 35.2. Si4010-C2 Rev. 1.0 149 ...

Page 150

... Si4010-C2 If pushbutton on keyfob development board, then it has to be isolated by R5 For debugging chain to work, LED must be isolated by R6 VBUS (+5V) Can be used to generate local VDD 1k R2 Figure 35.2. 14-Pin C2 ToolStick Connection to Device 150 VDD SW_GPIO4 R5 GPIO4 C2DAT 1k5 VDD LED R6 470 GPIO5 ...

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... RAM content with the user code will get erased. 2. The LED driver cannot be used when the device is connected to the debug adapters (USB debug adapter or a ToolStick). 3. Once the part is finalized, programmed as Run part, no further debugging is possible. Si4010-C2 Rev. 1.0 151 ...

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... Si4010-C2 36.2. Chip Shutdown Limitation While developing firmware on an unprogrammed chip the user cannot call the API function vSys_Shutdown() to shutdown the chip without loosing the RAM code downloaded by IDE. Instead, the user should comment out the call to the shutdown function and replace it with a temporary code, which monitors a button press, actually monitoring P0 and P1 port inputs based on the user current port settings ...

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... Disconnect the keyfob from the IDE by pressing the Disconnect button. The LED gets enabled and the application runs from the point where the application is currently halted. To run the application from the very beginning, the user must press Reset on the IDE before pressing Disconnect. Si4010-C2 Rev. 1.0 153 ...

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... AN511: Si4010 NVM Burner user's guide  AN515: Si4010 Key fob Development Kit Quick-Start Guide  AN518: Si4010 Memory Overlay Technique  AN526: Si4010 ROM 02.00 API Additional Library Description  AN577: Si4010 NVM Read Reliability Analysis  154 Rev. 1.0 ...

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... Updated section 36. Additional Reference  Resources to include new application notes Revision 0.5 to Revision 0.6 Removed revision B part numbers and replaced with  revision C part numbers Si4010-C2-GT and Si4010- C2-GS Revision 0.6 to Revision 1.0 Updated electrical specifications to final values.  Rev. 1.0 ...

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... Si4010- ONTACT NFORMATION Silicon Laboratories Inc. Silicon Laboratories Inc.  400 West Cesar Chavez  Austin, TX 78701  Please visit the Silicon Labs Technical Support web page:  https://www.silabs.com/support/pages/contacttechnicalsupport.aspx  and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice ...

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