T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 84
T48C862M-R4-TNQ
Manufacturer Part Number
T48C862M-R4-TNQ
Description
IC MON TIRE PRESS 433MHZ 24-SOIC
Manufacturer
Atmel
Datasheet
1.T48C862M-R4-TNS.pdf
(107 pages)
Specifications of T48C862M-R4-TNQ
Frequency
433MHz
Modulation Or Protocol
FM, FSK
Data Rate - Maximum
32 kBaud
Power - Output
10dBm
Current - Transmitting
9.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1KB EEPROM, 1KB RAM
Voltage - Supply
2 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Package / Case
24-SOIC (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Applications
-
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Combination Mode 9:
Biphase Demodulation
84
T48C862-R4 [Preliminary]
Figure 82. Manchester Demodulation
SSI mode 1:
Timer 3 mode 11: Biphase demodulation with Timer 3
In the Biphase demodulation mode the timer works like in the Manchester demodulation
mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop
samples the edge in the middle of the bitframe and the compare register 1 match event
shifts the toggle flip-flop output into shift register. Before activating the demodulation the
timer and the demodulation stage must be synchronized with the bitstream. The
Biphase code timing consists of parts with the half bitlength and the complete bitlength.
The synchronization routine must start the demodulator after an interval with the com-
plete bitlength.
The counter can be driven by any internal clock source and the output T3O can be used
by Timer 2 in this mode.
Figure 83. Biphase Demodulation
CM31=SCI
SR-DATA
CM31=SCI
SR-DATA
Counter 3
Timer 3
Timer 3
Q1=SI
mode
T3EX
mode
T3EX
Reset
T3I
T3I
SI
Synchronize
Synchronize
1
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
0
0
0
Bit 7
Bit 7
1
0
1
1
Bit 6
Bit 6
1
1
1
1
Manchester demodulation mode
Biphase demodulation mode
Bit 5
Bit 5
1
1
1
0
Bit 4
0
Bit 4
0
0
1
Bit 3
0
Bit 3
1
0
0
Bit 2
Bit 2
1
0
1
1
4551C–4BMCU–01/04
Bit 1
Bit 1
1
1
1
0
Bit 0
Bit 0
0
0
0
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