MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 70

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
11.2.1.2 RF channel redundancy and framing
11.2.1.3 Transmission of bit oriented frames
11.2.1.4 Transmission of frames with more than 64 bytes
Each ISO/IEC 14443 A frame transmitted consists of a Start Of Frame (SOF) pattern,
followed by the data stream and is closed by an End Of Frame (EOF) pattern. These
different phases of the transmission sequence can be monitored using the PrimaryStatus
register ModemState[2:0] bits; see
Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is
calculated and appended to the data stream. The CRC is calculated according to the
settings in the ChannelRedundancy register. Parity generation is handled according to the
ChannelRedundancy register ParityEn and ParityOdd bits settings.
The transmitter can be configured to send an incomplete last byte. To achieve this the
BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This
is shown in
Figure 14
register. All fully transmitted bytes are followed by a parity check bit but the incomplete
byte is not followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are
automatically cleared.
Remark: If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be
disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit.
To generate frames of more than 64 bytes, the microprocessor must write data to the
FIFO buffer while the Transmit command is active. The state machine checks the FIFO
buffer status when it starts transmitting the last bit of the data stream; the check time is
shown in
Fig 14. Transmitting bit oriented frames
TxLastBits = 0
TxLastBits = 7
TxLastBits = 1
Figure 15
shows the data stream when bit ParityEn is set in the ChannelRedundancy
Figure
All information provided in this document is subject to legal disclaimers.
14.
SOF
SOF
SOF
with arrows.
Rev. 3.3 — 15 March 2010
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0
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048033
Section 11.2.4 on page
Highly Integrated ISO/IEC 14443 A Reader IC
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MFRC500
© NXP B.V. 2010. All rights reserved.
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