M24LR64-RDW6T/2 STMicroelectronics, M24LR64-RDW6T/2 Datasheet - Page 27

• Manufacturer Part Number: M24LR64-RDW6T/2
• Description: 13.56MHZ 64KBIT EEPROM 8 TSSOP
• Manufacturer: STMicroelectronics

Specifications of M24LR64-RDW6T/2

• Featured Product: STM32 Cortex-M3 Companion Products
• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: 64 Kbit EEPROM
• Package / Case: 8-TSSOP
• Memory Size: 64 KB
• Organization: 2 K x 32
• Interface Type: I2C
• Maximum Clock Frequency: 400 KHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 600 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10487-2

M24LR64-R
4.5
4.5.1
Table 14.
1. Delivery state: I
M24LR64-R I
The M24LR64-R controls I
the 64-bit I2C_Write_Lock bit area. The I
commands: I
I
The I
M24LR64-R in order to modify the write access rights of all the memory sectors protected by
the I2C_Write_Lock bits, including the password itself. If the presented password is correct,
the access rights remain activated until the M24LR64-R is powered off or until a new I
Present Password command is issued.
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown
in
responds to each address byte with an acknowledge bit, and then waits for the 4 password
data bytes, the validation code, 09h, and a resend of the 4 password data bytes. The most
significant byte of the password is sent first, followed by the least significant bytes.
It is necessary to send the 32-bit password twice to prevent any data corruption during the
sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R does
not start the internal comparison.
When the bus master generates a Stop condition immediately after the Ack bit (during the
“10
condition at any other time does not trigger the internal delay. During that delay, the
M24LR64-R compares the 32 received data bits with the 32 bits of the stored I
If the values match, the write access rights to all protected sectors are modified after the
internal delay. If the values do not match, the protected sectors remains protected.
During the internal delay, Serial Data (SDA) is disabled internally, and the device does not
respond to any requests.
2
C Present Password command description
Figure
th
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
I
2
bit” time slot), an internal delay equivalent to the write cycle time is triggered. A Stop
2
C Present Password command is used in I
C byte address
8, and waits for two I
System parameter sector

C Present Password and I
2
C password= 0000 0000h, RF password = 0000 0000h,
2304
2308
2312
2316
2320
2324
2328
2332
2
C password security
2
C sector write access using the 32-bit-long I
DSFID (FFh)
Bits [31:24]
UID (E0h)
Doc ID 15170 Rev 12
2
C password address bytes 09h and 00h. The device
UID
2
2
Mem_Size (03 07FFh)
C Write Password.
C password value is managed using two I
Bits [23:16]
UID (02h)
AFI (00h)
2
UID
C mode to present the password to the
RF password 3
RF password 1
RF password 2
I
2
C password
ST reserved
Bits [15:8]
(1)
(1)
(1)
(1)
UID
UID
System memory area
2
C password and
2
IC Ref (2Ch)
ST reserved
C password.
Bits [7:0]
UID
UID
2
C
27/128
2
C