P5DF072EV2/T0PD409 NXP Semiconductors, P5DF072EV2/T0PD409 Datasheet - Page 3

• Manufacturer Part Number: P5DF072EV2/T0PD409
• Description: IC SAM MIFARE SAM AV1 8PLLCC
• Manufacturer: NXP Semiconductors

Specifications of P5DF072EV2/T0PD409

• Rf Type: Read / Write
• Frequency: 1MHz ~ 10MHz
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935285621118

NXP Semiconductors
6. Block diagram
7. Functional description
P5DF072EV2/T0PD4090_SDS_31
Product short data sheet
PUBLIC
Fig 1.
RST_N
CLK_N
IO1
Block diagram
C7
C3
C2
7.1 Contact interface
7.2 External clock frequency and bit rates
7.3 UID/serial number
CLOCK
FILTER
I/O
SECURITY SENSORS
RESET GENERATION
The pad assignment and the electrical characteristics are fully compliant with
ISO/IEC 7816 (part 2 and part 3). The MIFARE SAM AV1 operates with class A, class B
and class C interface devices. An internal charge pump provides the EEPROM
programming voltage. Note that pad C6 is not a programming voltage input but is an
output line for the clock signal for I
Pad C8 is used as the data line to the reader chip. These two pads for connection to the
MFRC52X are the only ones deviating from the ISO standard pin assignment.
The basic operating frequency of the MIFARE SAM AV1 is 3.5712 MHz. With this
frequency the standard bit rates can be reached using ISO/IEC 7816 transmission factors
F and D.
The maximum specified bit rate in all cases is 1.5 Mbit/s.
The SAM IC features a 7 byte unique serial number that is programmed into a locked part
of the non-volatile memory that is reserved for the manufacturer. This UID is fixed and
cannot be changed.
The UID can be obtained by using the SAM_GetVersion command.
REGULATOR
VOLTAGE
GENERATION
ISO 7816
CLOCK
UART
All information provided in this document is subject to legal disclaimers.
16-BIT
T0
Rev. 3.1 — 14 June 2010
TIMERS
ROM
16-BIT
T1
189731
CRC16
MICROPROCESSOR
2
MEMORY MANAGEMENT UNIT
C-bus communication to the MFRC52X reader chip.
SECURE
CORE
P5DF072EV2/T0PD4090
GENERATOR
RANDOM
NUMBER
TRUE
FAST
PROCESSOR
CRYPTO1
CO-
PROCESSOR
EEPROM
3DES
CO-
MIFARE SAM AV1
© NXP B.V. 2010. All rights reserved.
PROCESSOR
AES
CO-
RAM
001aal952
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