ATA556711-TASY Atmel, ATA556711-TASY Datasheet - Page 3

IC IDIC R/W 330BIT 0PF 8-SOIC

ATA556711-TASY

Manufacturer Part Number
ATA556711-TASY
Description
IC IDIC R/W 330BIT 0PF 8-SOIC
Manufacturer
Atmel
Series
ATA5567r
Datasheet

Specifications of ATA556711-TASY

Rf Type
Read / Write
Frequency
100kHz ~ 150kHz
Features
E5550, e5551, T5557 Binary Compatible
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4874F–RFID–07/08
Data-rate Generator
Write Decoder
HV Generator
DC Supply
Power-On Reset (POR)
Clock Extraction
Controller
Mode Register
The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or
equal to any of the fixed e5550/e5551 and T5554 bit rates (RF/8, RF/16, RF/32, RF/40, RF/50,
RF/64, RF/100, and RF/128).
This function decodes the write gaps and verifies the validity of the data stream according to the
Atmel e555x write method (pulse interval encoding).
This on-chip charge pump circuit generates the high voltage required for programming of the
EEPROM.
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu-
lates this RF source and uses it to generate its supply voltage.
This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.
The clock extraction circuit uses the external RF signal as its internal clock source.
The control-logic module executes the following functions:
The first two bits of the reader to tag data stream are the opcode, for example, write, direct
access, or reset.
In password mode, the 32 bits received after the opcode are compared with the password stored
in memory block 7.
The mode register stores the configuration data from the EEPROM block 0. It is continually
refreshed at the start of every block read and (re-)loaded after any POR event or reset com-
mand. On delivery, the mode register is preprogrammed with the value 0014 8000h which
corresponds to continuous read of block 0, Manchester coded, RF/64.
• Loads mode register with configuration data from EEPROM block 0 after power-on and also
• Controls memory access (read, write)
• Handles write data transmission and write error modes
during reading
ATA5567
3

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