73M1903-IM/F Maxim Integrated Products, 73M1903-IM/F Datasheet - Page 4

• Manufacturer Part Number: 73M1903-IM/F
• Description: IC MODEM AFE V.22BIS 32-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903-IM/F

• Number Of Channels: 2
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Bits: -

same pin out. The following table describes the function of each pin. There are two pairs of power
supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply
73M1903 Data Sheet
1 Signal Description
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately
isolate and decouple these supplies will compromise device performance.
4
Pin Name
VND
VNA
VPD
VPA
VPPLL
VNPLL
RST
OSCIN
OSCOUT
GPIO(0-7)
VREF
RXAP
RXAN
TXAP
TXAN
SCLK
SDOUT
SDIN
FS
TYPE
SckMode
Type
PWR
PWR
PWR
PWR
GND
GND
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
3, 4, 5, 6,
24,30,31
32QFN
Pin #
1,22
2,25
23,
16
10
20
17
19
18
13
15
14
12
11
32
29
27
28
9
8
7
20VT
Pin#
2,18
N/A
NA
13
17
14
16
15
12
11
10
20
19
3
8
7
6
9
5
1
4
Positive Digital Supply
Positive Analog Supply
Positive PLL Supply, shared with VPD
source, drive OSCIN.
Software definable digital input/output pins. Not available in
the 20VT (TSSOP) package.
(mode1); tied low = late (mode0).
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not available in 20VT.
Negative Digital Ground
Negative Analog Ground
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high- default.
Crystal oscillator input. When providing an external clock
Reference voltage pin (Reflects VREF).
Receive analog positive input.
Receive analog negative input.
Transmit analog positive output.
Transmit analog negative output.
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
Serial data output (or input to the host).
Serial data input (or output from the host).
Frame synchronization. (Active Low)
Type of frame sync. Open, weak-pulled high = early
Controls the SCLK behavior after FS. Open, weak-pulled
Crystal oscillator circuit output pin.
Description
DS_1903_032
Rev. 2.1