73M1903-IM/F Maxim Integrated Products, 73M1903-IM/F Datasheet - Page 6

• Manufacturer Part Number: 73M1903-IM/F
• Description: IC MODEM AFE V.22BIS 32-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903-IM/F

• Number Of Channels: 2
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Bits: -

set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data
contained in the register pointed to by address bits A6-A0. Only one control frame can occur between
any two data frames.
Writes to unimplemented registers are ignored. Reading an unimplemented register returns a value of 0.
The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is set to a 0
the control frames occur mid way between data frames, i.e., the time between data frames is equal. If
SPOS is set to a 1, the control frame is ¼ of the way between consecutive data frames, i.e., the control
frame is closer to the first data frame. This is illustrated in
New to the 73M1903 modem AFE IC is a feature that shuts off the serial clock (SCLK) after 32 cycles of
SCLK following the frame synch
73M1903 Data Sheet
The bits transmitted on the SDOUT pin are defined as follows:
If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN
are defined as follows:
In this case TX0=0 is forced.
If the Hardware Control bit (bit 0 of register 01h) is set to one, the 16 bits that are received on the SDIN
input are defined as follows:
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit
code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data
frames. If the hardware control bit is set to zero, CTL (TX bit 0) is used by software to request a control
frame. If CTL is high, a control frame is initiated before the next data frame. A control frame allows the
controller to read or write status and control to the 73M1903.
The control word received on the SDIN pin is defined as follows:
The control word transmitted on the SDOUT pin is defined as follows:
If the R/W bit is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received
on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is
option. This mode is controlled by the SckMode pin. If this pin is left open, the clock will run
continuously. If SckMode is low the clock will be gated on for 32 clocks for each FS. The SDOUT and FS
pins change values following a rising edge of SCLK. The SDIN pin is sampled on the falling edge of
SCLK.
6
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
TX15 TX14 TX13 TX12 TX11 TX10 TX9
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
TX15 TX14 TX13 TX12 TX11 TX10 TX9
R/W
0
Figure 4
A6
0
A5
0
shows the timing diagrams for the serial port.
A4
0
A3
0
(Figure
A2
0
1). This feature is unavailable in the 20 TSSOP package
A1
0
Bit8
Bit8
TX8
Bit8
TX8
Bit8
Bit8
A0
0
Bit7
Bit7
TX7
Bit7
TX7
Bit7
Bit7
D7
D7
Figure
Bit6
Bit6
TX6
Bit6
TX6
Bit6
Bit6
D6
D6
2.
Bit5
Bit5
TX5
Bit5
TX5
Bit5
Bit5
D5
D5
Bit4
Bit4
TX4
Bit4
TX4
Bit4
Bit4
D4
D4
Bit3
Bit3
TX3
Bit3
TX3
Bit3
Bit3
D3
D3
Bit2
Bit2
TX2
Bit2
TX2
Bit2
Bit2
D2
D2
DS_1903_032
Bit1
Bit1
TX1
Bit1
TX1
Bit1
Bit1
D1
D1
Rev. 2.1
Bit0
Bit0
CTL
Bit0
TX0
Bit0
Bit0
D0
D0